Patents by Inventor Thomas Boesch
Thomas Boesch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210372768Abstract: An auxiliary measuring instrument, configured to form together with a ground-based surveying device having range-and-direction measuring functionality, a system for surveying or staking out object points, wherein the auxiliary measuring instrument including a handheld main body of a defined length, and a man-machine interface, wherein the auxiliary measuring instrument is designed in a pen-like form and size and is configured to aim at an object point to be surveyed or staked out in a one-handed manner with a first end of the auxiliary measuring instrument and wherein a body is attached at a second end of the auxiliary measuring instrument, wherein the body is designed for optical-image-based determination of the position of the auxiliary measuring instrument by the surveying device.Type: ApplicationFiled: October 31, 2018Publication date: December 2, 2021Applicant: LEICA GEOSYSTEMS AGInventors: Josef MÜLLER, Jochen SCHEJA, Oliver FAIX, Thomas BÖSCH, Claudio ISELI, Hannes MAAR, Patrik LENGWEILER, Markus GESER
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Publication number: 20210264250Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Inventors: Surinder Pal SINGH, Thomas BOESCH, Giuseppe DESOLI
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Publication number: 20210256346Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.Type: ApplicationFiled: February 18, 2020Publication date: August 19, 2021Inventors: Giuseppe DESOLI, Carmine CAPPETTA, Thomas BOESCH, Surinder Pal SINGH, Saumya SUNEJA
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Publication number: 20210241806Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.Type: ApplicationFiled: January 26, 2021Publication date: August 5, 2021Inventors: Nitin CHAWLA, Thomas BOESCH, Anuj Grover, Surinder Pal SINGH, Giuseppe DESOLI
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Publication number: 20210223042Abstract: A geodetic instrument, e.g. a total station, laser scanner, laser tracker or laser level, for example for construction works. The geodetic instrument is separated into a static base part and a rotatable targeting part. The base part comprises a power unit for powering the geodetic instrument and the targeting part comprises a surveying and/or projection module for geodetic surveying and/or projection in a changeable target direction. Any change of the target direction is effected with the base part remaining static wherefore the targeting part is rotatable relative to the base part. The base part inertia is equal to or greater than the target part inertia.Type: ApplicationFiled: January 21, 2021Publication date: July 22, 2021Applicant: LEICA GEOSYSTEMS AGInventors: Johannes HOTZ, Thomas BÖSCH, Josef MÜLLER
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Publication number: 20210192833Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.Type: ApplicationFiled: March 5, 2021Publication date: June 24, 2021Inventors: Surinder Pal SINGH, Thomas BOESCH, Giuseppe DESOLI
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Publication number: 20210181828Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.Type: ApplicationFiled: December 3, 2020Publication date: June 17, 2021Inventors: Nitin CHAWLA, Anuj GROVER, Giuseppe DESOLI, Kedar Janardan DHORI, Thomas BOESCH, Promod KUMAR
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Publication number: 20210181494Abstract: An apparatus for inserting a measurement light beam which can be projected onto a target object, comprising a light-refracting component having an optical axis, and at least two mirrors for deflecting the measurement light beam, and an optical overall body consisting of at least one optically effective material, wherein the optical overall body is configured in such a way that the at least two mirrors are fitted inside or at the edge, in particular as a part, of the optical overall body, in such a way that the measurement light beam entering the optical overall body is offset parallel to the incident measurement light beam when emerging from the optical overall body, so that the emerging measurement light beam lies on the optical axis of the light-refracting component of the apparatus and is projected in this form onto the target object.Type: ApplicationFiled: December 11, 2020Publication date: June 17, 2021Applicant: LEICA GEOSYSTEMS AGInventors: Thomas BÖSCH, Josef MÜLLER
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Patent number: 10977854Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes.Type: GrantFiled: February 20, 2019Date of Patent: April 13, 2021Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.Inventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
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Publication number: 20210081773Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.Type: ApplicationFiled: September 16, 2020Publication date: March 18, 2021Inventors: Nitin CHAWLA, Giuseppe DESOLI, Manuj AYODHYAWASI, Thomas BOESCH, Surinder Pal SINGH
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Publication number: 20210073450Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.Type: ApplicationFiled: November 10, 2020Publication date: March 11, 2021Inventors: Thomas BOESCH, Giuseppe DESOLI
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Publication number: 20210072894Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: ApplicationFiled: September 4, 2020Publication date: March 11, 2021Inventors: Nitin CHAWLA, Giuseppe DESOLI, Anuj GROVER, Thomas BOESCH, Surinder Pal SINGH, Manuj AYODHYAWASI
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Patent number: 10872186Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.Type: GrantFiled: August 23, 2019Date of Patent: December 22, 2020Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Thomas Boesch, Giuseppe Desoli
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Publication number: 20200310758Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.Type: ApplicationFiled: March 27, 2020Publication date: October 1, 2020Inventors: Giuseppe DESOLI, Thomas BOESCH, Carmine CAPPETTA, Ugo Maria IANNUZZI
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Publication number: 20200310761Abstract: A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m?1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m?1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.Type: ApplicationFiled: March 27, 2020Publication date: October 1, 2020Inventors: Michele ROSSI, Giuseppe DESOLI, Thomas BOESCH, Carmine CAPPETTA
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Publication number: 20200272779Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.Type: ApplicationFiled: May 13, 2020Publication date: August 27, 2020Inventors: Thomas BOESCH, Giuseppe DESOLI
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Patent number: 10726177Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.Type: GrantFiled: July 19, 2019Date of Patent: July 28, 2020Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Thomas Boesch, Giuseppe Desoli
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Patent number: 10712154Abstract: A laser level comprising a first laser module and a second laser module, each comprising a laser diode and an optical unit, a holder arranging the first laser module and the second laser module in a fixed relative position, and a housing, in which the holder is suspended with a gimbal or ball joint. Each optical unit comprises a collimating lens arranged along the beam path following the laser diode, and configured for collimating a beam emitted by the laser diode; a pair of partially transmitting mirrors, each arranged along the beam path following the collimating lens, and configured for laterally reflecting less than half of the collimated beam in terms of the beam cross-section, and in terms of the beam intensity; and a cylindrical lens arranged along the beam path following the pair of partially transmitting mirrors, and configured for shaping the collimated beam into a fan beam.Type: GrantFiled: July 6, 2018Date of Patent: July 14, 2020Assignee: LEICA GEOSYSTEMS AGInventors: Kai Fei, Guanghua Ma, Thomas Bösch
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Publication number: 20190377840Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.Type: ApplicationFiled: August 23, 2019Publication date: December 12, 2019Inventors: Thomas BOESCH, Giuseppe DESOLI
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Publication number: 20190340314Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Inventors: Thomas BOESCH, Giuseppe DESOLI