Patents by Inventor Thomas Christopher Cecil

Thomas Christopher Cecil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11762283
    Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern (110).
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: September 19, 2023
    Assignee: Synopsys, Inc.
    Inventors: Amyn A. Poonawala, Jason Jiale Shu, Thomas Christopher Cecil
  • Patent number: 11748553
    Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: September 5, 2023
    Assignee: Synopsys, Inc.
    Inventor: Thomas Christopher Cecil
  • Patent number: 11663485
    Abstract: A system performs distributed or parallel pattern extraction and clustering for pattern classification of large layouts of electronic circuits. The system identifies circuit patterns with a layout representation. The system encodes the circuit patterns using a neural network based autoencoder to generate encoded circuit patterns that can be stored efficiently. The system clusters the encoded circuit patterns into an arbitrary number of clusters based upon a high degree of similarity. The clusters of circuit patterns may be used for training and evaluation of machine learning based models.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 30, 2023
    Assignee: Synopsys, Inc.
    Inventor: Thomas Christopher Cecil
  • Publication number: 20230129457
    Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventor: Thomas Christopher Cecil
  • Patent number: 11568127
    Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 31, 2023
    Assignee: Synopsys, Inc.
    Inventor: Thomas Christopher Cecil
  • Publication number: 20220277130
    Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.
    Type: Application
    Filed: January 10, 2022
    Publication date: September 1, 2022
    Inventor: Thomas Christopher Cecil
  • Publication number: 20220276554
    Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 1, 2022
    Inventors: Thomas Christopher Cecil, Kevin Hooker
  • Patent number: 11360382
    Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: June 14, 2022
    Assignee: Synopsys, Inc.
    Inventors: Thomas Christopher Cecil, Kevin Hooker
  • Patent number: 11222160
    Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: January 11, 2022
    Assignee: Synopsys, Inc.
    Inventor: Thomas Christopher Cecil
  • Publication number: 20210181620
    Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern (110).
    Type: Application
    Filed: November 23, 2020
    Publication date: June 17, 2021
    Inventors: Amyn A. POONAWALA, Jason Jiale SHU, Thomas Christopher CECIL
  • Publication number: 20210064977
    Abstract: A system uses machine learning models, such as neural networks for generating mask design from a circuit design. The machine learning models have inputs and outputs which are localized to a small region of the circuit design. The machine learning model takes as input features describing the circuit design in the neighborhood of a location and generates an offset distance as output. The system uses the offset distance to generate features of the mask design, for example, main features or assist features corresponding to a circuit design polygon. The system may use the offset distance for target optimization by modifying the circuit design polygon to obtain a circuit design polygon that has improved manufacturability.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 4, 2021
    Inventors: Thomas Christopher Cecil, Kevin Hooker, Marco Guajardo
  • Publication number: 20210018831
    Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 21, 2021
    Inventors: Thomas Christopher Cecil, Kevin Hooker
  • Publication number: 20200387660
    Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 10, 2020
    Inventor: Thomas Christopher Cecil
  • Publication number: 20200372365
    Abstract: A system performs distributed or parallel pattern extraction and clustering for pattern classification of large layouts of electronic circuits. The system identifies circuit patterns with a layout representation. The system encodes the circuit patterns using a neural network based autoencoder to generate encoded circuit patterns that can be stored efficiently. The system clusters the encoded circuit patterns into an arbitrary number of clusters based upon a high degree of similarity. The clusters of circuit patterns may be used for training and evaluation of machine learning based models.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 26, 2020
    Inventor: Thomas Christopher Cecil
  • Patent number: 10430543
    Abstract: A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector.
    Type: Grant
    Filed: October 4, 2014
    Date of Patent: October 1, 2019
    Assignee: Synopsys, Inc.
    Inventor: Thomas Christopher Cecil
  • Patent number: 10318697
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Publication number: 20170032076
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Application
    Filed: October 10, 2016
    Publication date: February 2, 2017
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Patent number: 9471746
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 18, 2016
    Assignee: Synopsys, Inc.
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Publication number: 20160098511
    Abstract: A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector.
    Type: Application
    Filed: October 4, 2014
    Publication date: April 7, 2016
    Inventor: Thomas Christopher Cecil
  • Publication number: 20160042118
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 11, 2016
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter