Patents by Inventor Thomas Christopher Cecil

Thomas Christopher Cecil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160042118
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 11, 2016
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Patent number: 9170481
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 27, 2015
    Assignee: Synopsys, Inc.
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Publication number: 20140282290
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Synopsys, Inc.
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter