Patents by Inventor Thomas D. Happ

Thomas D. Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9111609
    Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 18, 2015
    Assignees: International Business Machines Corporation, Qimonda AG
    Inventors: Thomas D. Happ, Alejandro G. Schrott
  • Publication number: 20120134204
    Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 31, 2012
    Applicants: QIMONDA NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas D. Happ, Alejandro G. Schrott
  • Patent number: 8138028
    Abstract: A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: March 20, 2012
    Assignees: Macronix International Co., Ltd, International Business Machines Corporation, Qimonda North America Corp.
    Inventors: Hsiang Lan Lung, Chieh Fang Chen, Yi Chou Chen, Shih Hung Chen, Chung Hon Lam, Eric Andrew Joseph, Alejandro Gabriel Schrott, Matthew J. Breitwisch, Geoffrey William Burr, Thomas D. Happ, Jan Boris Philipp
  • Patent number: 8124950
    Abstract: A memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: February 28, 2012
    Assignees: International Business Machines Corporation, Qimonda North America Corp.
    Inventors: Thomas D. Happ, Alejandro G. Schrott
  • Patent number: 8030634
    Abstract: A memory array with self-centered diode access devices results from a process in which diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 4, 2011
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation, Qimonda AG
    Inventors: Hsiang-Lan Lung, Min Yang, Thomas D. Happ, Bipin Rajendran
  • Patent number: 7825398
    Abstract: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than that of the base portion. A memory element is on a top surface of the pillar portion of the bottom electrode, and a top electrode is on the memory element. A dielectric spacer contacts the outer surface of the pillar portion, the outer surface of the base portion of the bottom electrode self-aligned with an outer surface of the dielectric spacer.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: November 2, 2010
    Assignees: Macronix International Co., Ltd., Qimonda A.G.
    Inventors: Thomas D. Happ, Yi-Chou Chen, Jan Boris Philipp, Hsiang-Lan Lung
  • Patent number: 7795109
    Abstract: Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: September 14, 2010
    Assignee: Qimonda AG
    Inventors: Rolf Weis, Thomas D. Happ
  • Patent number: 7787279
    Abstract: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: August 31, 2010
    Assignee: Qimonda AG
    Inventors: Thomas D. Happ, Cay-Uwe Pinnow, Ralf Symanczyk, Klaus-Dieter Ufert
  • Publication number: 20100054029
    Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, QIMONDA NORTH AMERICA CORP.
    Inventors: Thomas D. Happ, Alejandro G. Schrott
  • Publication number: 20100019215
    Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of word lines extending in a first direction, and a plurality of bit lines overlying the plurality of word lines and extending in a second direction. A plurality of memory cells are at cross-point locations. Each memory cell comprises a diode having first and second sides aligned with sides of a corresponding word line. Each memory cell also includes a bottom electrode self-centered on the diode, the bottom electrode having a top surface with a surface area less than that of the top surface of the diode. Each of the memory cells includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material underlying and in electrical communication with a corresponding bit line.
    Type: Application
    Filed: July 22, 2008
    Publication date: January 28, 2010
    Applicants: Macronix International Co., Ltd., Qimonda North America Corp., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Chung Hon Lam, Thomas D. Happ, Matthew J. Breitwisch, Alejandro Gabriel Schrott, Min Yang
  • Publication number: 20090315090
    Abstract: Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material.
    Type: Application
    Filed: June 23, 2008
    Publication date: December 24, 2009
    Inventors: Rolf Weis, Thomas D. Happ
  • Publication number: 20090267042
    Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of resistance changing memory cells is provided. Each memory cell includes: a semiconductor substrate; a select device arranged within the semiconductor substrate; and a memory element being arranged above the semiconductor substrate. The select device is a diode comprising a first semiconductor area of a first conductive type and a second semiconductor area of a second conductive type which are arranged adjacent to each other such that a lateral pn-junction is formed. The first semiconductor area is connected to a word line arranged on or above the semiconductor substrate. The second semiconductor area is connected to the memory element via a conductive connection element.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 29, 2009
    Inventors: Thomas D. Happ, Igor Kasko, Andreas Walter
  • Publication number: 20090251944
    Abstract: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than that of the base portion. A memory element is on a top surface of the pillar portion of the bottom electrode, and a top electrode is on the memory element. A dielectric spacer contacts the outer surface of the pillar portion, the outer surface of the base portion of the bottom electrode self-aligned with an outer surface of the dielectric spacer.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: Macronix International Co., Ltd.
    Inventors: Thomas D Happ, Yi-Chou Chen, Jan Boris Philipp, Hsiang-Lan Lung
  • Publication number: 20090242865
    Abstract: A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned vias are formed over the diodes. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Applicants: Macronix International Co., Ltd, Qimonda AG, International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Min Yang, Thomas D. Happ, Bipin Rajendran
  • Patent number: 7515461
    Abstract: A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: April 7, 2009
    Assignees: Macronix International Co., Ltd., Qimonda North America Corporation
    Inventors: Thomas D. Happ, Hsiang-Lan Lung, Thomas Nirschl
  • Patent number: 7414257
    Abstract: The present invention relates to a switching device to be irreversibly switched from an electrically isolating off-state into an electrically conducting on-state for use in a configurable interconnect, comprising two separate electrodes, at least one of which being a reactive metal electrode, and a solid state electrolyte arranged between said electrodes and being capable of electrolyte isolating said electrodes to define said off-state, said electrodes and said solid state electrolyte forming a redox-system having a mini-mum voltage (“turn-on voltage”) to start a redox reaction, the redox reaction resulting in the generation of metal ions to be released into said solid state electrolyte, the metal ions being reduced to increase a metal concentration within said solid state electrolyte, wherein an increase of said metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 19, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas D. Happ, Thomas Roehr
  • Publication number: 20080191187
    Abstract: A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
    Type: Application
    Filed: June 18, 2007
    Publication date: August 14, 2008
    Applicants: MACRONIX INTERNATIONAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, QIMONDA NORTH AMERICA CORP.
    Inventors: HSIANG LAN LUNG, CHIEH-FANG CHEN, YI-CHOU CHEN, SHIH HUNG CHEN, CHUNG HON LAM, ERIC ANDREW JOSEPH, ALEJANDRO GABRIEL SCHROTT, MATTHEW J. BREITWISCH, GEOFFREY WILLIAM BURR, THOMAS D. HAPP, JAN BORIS PHILIPP
  • Publication number: 20080165570
    Abstract: A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Applicant: Macronix International Co., Ltd.
    Inventors: Thomas D. Happ, Hsiang Lan Lung, Thomas Nirschl
  • Patent number: 7337282
    Abstract: According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and the same memory component, is provided, the process comprising the steps: Sending out a signal to select one of several possible modes for the memory component; and Operating the memory component in accordance with the specific mode selected by the signal.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: February 26, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas D. Happ, Michael Kund, Ralf Symanczyk
  • Patent number: 7215564
    Abstract: A programmable metallization memory cell with a storage region (3) formed from a chalcogenide glass and an electrode (4) which is preferably silver is located at the crossing point of a respective bit line (1) and a respective word line (2). There is a pn junction between the bit lines (1) and the chalcogenide glass.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 8, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thomas D. Happ, Ralf Symanczyk