Patents by Inventor Thomas E. Grebs

Thomas E. Grebs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8884365
    Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8816429
    Abstract: Charge balanced semiconductor devices with increased mobility structures and methods for making and using such devices are described. The semiconductor devices contain a substrate heavily doped with a dopant of a first conductivity type, a strained region containing a strain dopant in an upper portion of the substrate, an epitaxial layer being lightly doped with a dopant of a first or second conductivity type on the strained region, a trench formed in the epitaxial layer with the trench containing a MOSFET structure having a drift region overlapping the strained region, a source layer contacting an upper surface of the epitaxial layer and an upper surface of the MOSFET structure, and a drain contacting a bottom portion of the substrate. Since the drift region of the MOSFET structure is formed from the strained region in the substrate, the mobility of the drift region is improved and allows higher current capacity for the trench MOSFET devices. Other embodiments are described.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: August 26, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Thomas E. Grebs
  • Patent number: 8803207
    Abstract: In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: August 12, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Nathan Lawrence Kraft, Rodney Ridley, Gary M. Dolny, Joseph A. Yedinak, Christopher Boguslaw Kocon, Ashok Challa
  • Publication number: 20130248991
    Abstract: A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 26, 2013
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Hamza YILMAZ, Daniel CALAFUT, Christopher Boguslaw KOCON, Steven P. SAPP, Dean E. PROBST, Nathan L. KRAFT, Thomas E. GREBS, Rodney S. RIDLEY, Gary M. DOLNY, Bruce D. MARCHANT, Joseph A. YEDINAK
  • Patent number: 8502314
    Abstract: This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: August 6, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Jayson S. Preece
  • Patent number: 8492837
    Abstract: Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: July 23, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Thomas E. Grebs, John L. Benjamin
  • Patent number: 8461040
    Abstract: A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: June 11, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Rodney S. Ridley, Nathan Lawrence Kraft
  • Patent number: 8441069
    Abstract: A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 14, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8432000
    Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: April 30, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Thomas E. Grebs
  • Publication number: 20130009237
    Abstract: Charge balanced semiconductor devices with increased mobility structures and methods for making and using such devices are described. The semiconductor devices contain a substrate heavily doped with a dopant of a first conductivity type, a strained region containing a strain dopant in an upper portion of the substrate, an epitaxial layer being lightly doped with a dopant of a first or second conductivity type on the strained region, a trench formed in the epitaxial layer with the trench containing a MOSFET structure having a drift region overlapping the strained region, a source layer contacting an upper surface of the epitaxial layer and an upper surface of the MOSFET structure, and a drain contacting a bottom portion of the substrate. Since the drift region of the MOSFET structure is formed from the strained region in the substrate, the mobility of the drift region is improved and allows higher current capacity for the trench MOSFET devices. Other embodiments are described.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventor: Thomas E. Grebs
  • Patent number: 8319290
    Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Thomas E. Grebs
  • Publication number: 20120267711
    Abstract: This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Inventors: Thomas E. Grebs, Jayson S. Preece
  • Publication number: 20120220091
    Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
    Type: Application
    Filed: March 12, 2012
    Publication date: August 30, 2012
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
  • Patent number: 8227855
    Abstract: Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: July 24, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph Yedinak, Mark Rinehimer, Thomas E. Grebs, John Benjamin
  • Publication number: 20120153384
    Abstract: A semiconductor package device houses a die which comprises a power device, and the die further includes a silicon region over a substrate, a first plurality of trenches extending in the silicon region; a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the sinker trench extending from a top surface of the die through the silicon region, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench; and a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the sinker trench.
    Type: Application
    Filed: January 10, 2012
    Publication date: June 21, 2012
    Inventors: Thomas E. Grebs, Gary M. Dolny
  • Publication number: 20120104490
    Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 3, 2012
    Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven P. Sapp, Dean E. Probst, Nathan L. Kraft, Thomas E. Grebs, Rodney S. Ridley, Gary M. Dolny, Bruce D. Marchant, Joseph A. Yedinak
  • Patent number: 8148749
    Abstract: Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: April 3, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Mark Rinehimer, Joseph Yedinak, Dean E. Probst, Gary Dolny, John Benjamin
  • Patent number: 8148233
    Abstract: A semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate, and a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 3, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Gary M. Dolny
  • Patent number: 8143123
    Abstract: A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Rodney S. Ridley, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Christopher B. Kocon
  • Publication number: 20120058615
    Abstract: A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
    Type: Application
    Filed: March 7, 2011
    Publication date: March 8, 2012
    Inventors: Bruce Douglas Marchant, Thomas E. Grebs, Rodney S. Ridley, Nathan Lawrence Kraft