Patents by Inventor Thomas E. Seidel

Thomas E. Seidel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10996562
    Abstract: Structures and associated methods for making smaller physical feature sizes for masks used in imprint lithography for application to patterning for advanced semiconductor and data storage devices.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 4, 2021
    Inventor: Thomas E. Seidel
  • Patent number: 10923359
    Abstract: Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: February 16, 2021
    Inventors: Thomas E Seidel, Michael I Current
  • Publication number: 20210020452
    Abstract: Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 21, 2021
    Inventors: Thomas E Seidel, Michael I Current
  • Patent number: 10896823
    Abstract: Processes for localized film deposition on semiconductor device surfaces having non-planar features. The processes use combinations of Limited-Dose Atomic Layer Etch, Limited Dose Atomic Layer Deposition, and Atomic Layer Deposition to provide localized coatings only near or on the bottom, or only near the center, or only near or on the top and bottom of trench and Fin features.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: January 19, 2021
    Inventors: Thomas E. Seidel, Michael Current
  • Publication number: 20200161140
    Abstract: Processes for localized film deposition on semiconductor device surfaces having non-planar features. The processes use combinations of Limited-Dose Atomic Layer Etch, Limited Dose Atomic Layer Deposition, and Atomic Layer Deposition to provide localized coatings only near or on the bottom, or only near the center, or only near or on the top and bottom of trench and Fin features.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 21, 2020
    Inventors: Thomas E. Seidel, Michael Current
  • Publication number: 20190049839
    Abstract: Structures and associated methods for making smaller physical feature sizes for masks used in imprint lithography for application to patterning for advanced semiconductor and data storage devices.
    Type: Application
    Filed: October 15, 2018
    Publication date: February 14, 2019
    Inventor: Thomas E. Seidel
  • Patent number: 10156786
    Abstract: Structures and associated methods for making high index of refraction surface coatings for masks used in imprint lithography for application to patterning for advanced semiconductor and data storage devices.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: December 18, 2018
    Inventor: Thomas E. Seidel
  • Publication number: 20170090282
    Abstract: Structures and associated methods for making high index of refraction surface coatings for masks used in imprint lithography for application to patterning for advanced semiconductor and data storage devices.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 30, 2017
    Inventor: Thomas E. Seidel
  • Publication number: 20160379828
    Abstract: A conformal thermal ALD film having a combination of elements containing a dopant, such as boron (or phosphorus), and an oxide (or nitride), in intimate contact with a semiconductor substrate said combination having stable ambient and thermal annealing properties providing a shallow (less than ˜100 A) diffused (or recoil implanted) dopant, such as boron (or phosphorus) profile, into the underlying semiconductor substrate.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 29, 2016
    Inventors: Anil U. Mane, Thomas E. Seidel, Michael I. Current, Alexander Goldberg, Jeffrey W. Elam
  • Patent number: 7981473
    Abstract: A process in which a wafer is exposed to a first chemically reactive precursor dose insufficient to result in a maximum saturated ALD deposition rate on the wafer, and then to a second chemically reactive precursor dose, the precursors being distributed in a manner so as to provide substantially uniform film deposition. The second chemically reactive precursor dose may likewise be insufficient to result in a maximum saturated ALD deposition rate on the wafer or, alternatively, sufficient to result in a starved saturating deposition on the wafer. The process may or may not include purges between the precursor exposures, or between one set of exposures and not another.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: July 19, 2011
    Assignee: Aixtron, Inc.
    Inventors: Gi Youl Kim, Anuranjan Srivastava, Thomas E. Seidel, Ana R. Londergan, Sasangan Ramanathan
  • Publication number: 20100012036
    Abstract: An MSW processing apparatus includes two or more semi-isolated reaction chambers separated from one another by isolation regions configured with two or more TIG elements, either or both of which may be independently purged. The TIG elements may be configured in a staircase-like fashion and include vertical and horizontal conductance spacings, sized so that, under different operational process temperatures of the MSW processing apparatus, a change in the horizontal conductance spacing is less than a change in the vertical conductance spacing.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 21, 2010
    Inventors: Hugo Silva, Martin Dauelsberg, Johannes Lindner, Thomas E. Seidel, Gerhard K. Strauch
  • Publication number: 20080131601
    Abstract: A process in which a wafer is exposed to a first chemically reactive precursor dose insufficient to result in a maximum saturated ALD deposition rate on the wafer, and then to a second chemically reactive precursor dose, the precursors being distributed in a manner so as to provide substantially uniform film deposition. The second chemically reactive precursor dose may likewise be insufficient to result in a maximum saturated ALD deposition rate on the wafer or, alternatively, sufficient to result in a starved saturating deposition on the wafer. The process may or may not include purges between the precursor exposures, or between one set of exposures and not another.
    Type: Application
    Filed: March 1, 2004
    Publication date: June 5, 2008
    Inventors: Gi Youl Kim, Anuranjan Srivastava, Thomas E. Seidel, Ana R. Londergan, Sasangan Ramanathan
  • Patent number: 7183649
    Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: February 27, 2007
    Assignee: Genus, Inc.
    Inventors: Ana R. Londergan, Thomas E. Seidel
  • Patent number: 7164203
    Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: January 16, 2007
    Assignee: Genus, Inc.
    Inventors: Ana R. Londergan, Thomas E. Seidel
  • Patent number: 7129580
    Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: October 31, 2006
    Assignee: Genus, Inc.
    Inventors: Ana R. Londergan, Thomas E. Seidel
  • Patent number: 6905547
    Abstract: An apparatus with a processing chamber subjects a substrate to atomic layer deposition and deposits a film layer. The processing chamber includes at least a first gas switching port. A gas switching manifold is coupled to the processing chamber and configured to mix reactants with a neutral carrier gas and provide gas switching functionality for ALD processes. An upstream gas source and pressure setting apparatus is coupled to the gas switching manifold. The upstream gas source and pressure setting apparatus includes at least a first reactant source, a second reactant source and a neutral gas source. Additionally, the upstream gas source and pressure setting apparatus is configured to provide a cascade of continuing, decreasing pressures.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: June 14, 2005
    Assignee: Genus, Inc.
    Inventors: Ana R. Londergan, Thomas E. Seidel, Lawrence D. Matthysse, Ed C. Lee
  • Patent number: 6902624
    Abstract: A method and apparatus for the use of individual vertically stacked ALD or CVD reactors. Individual reactors are independently operable and maintainable. The gas inlet and output are vertically configured with respect to the reactor chamber for generally axi-symmetric process control. The chamber design is modular in which cover and base plates forming the reactor have improved flow design.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: June 7, 2005
    Assignee: Genus, Inc.
    Inventors: Thomas E. Seidel, Adrian Jansz, Jurek Puchacz, Ken Doering
  • Patent number: 6897119
    Abstract: A method and apparatus for performing atomic layer deposition in which a surface of a substrate is pretreated to make the surface of the substrate reactive for performing atomic layer deposition.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: May 24, 2005
    Assignee: Genus, Inc.
    Inventors: Ofer Sneh, Thomas E. Seidel, Carl Galewski
  • Patent number: 6720259
    Abstract: A method to deposit a passivating layer of a first material on an interior reactor surface of a cold or warm wall reactor, in which the first material is non-reactive with one or more precursor used to form a second materials. Subsequently when a film layer is deposited on a substrate by subjecting the substrate to the one or more precursors, in which at least one precursor has a low vapor pressure, uniformity and repeatability is improved by the passivation layer.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: April 13, 2004
    Assignee: Genus, Inc.
    Inventors: Ana R. Londergan, Sasangan Ramanathan, Jereld Winkler, Thomas E. Seidel
  • Publication number: 20040023516
    Abstract: A method to deposit a passivating layer of a first material on an interior reactor surface of a cold or warm wall reactor, in which the first material is non-reactive with one or more precursors used to form a second material. Subsequently when a film layer is deposited on a substrate by subjecting the substrate to the one or more precursors, in which at least one precursor has a low vapor pressure, uniformity and repeatability is improved by the passivation layer.
    Type: Application
    Filed: October 2, 2002
    Publication date: February 5, 2004
    Inventors: Ana R. Londergan, Sasangan Ramanathan, Jereld Winkler, Thomas E. Seidel