Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.

Abstract: Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.

Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.

Abstract: Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.

Abstract: Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.

Abstract: A projection display may use pulse width modulation wherein the duty cycle may be varied. This duty cycle variation may improve bit depth in some embodiments. For example, on alternate frames, the duty cycle may be reduced by a given percentage.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.

Abstract: A light modulator such as an SLM, in which the pixel data array is decoupled from the pixel display array. The pixel data array can be located externally, permitting significant reduction in the circuitry present under each pixel of the display, in turn permitting significant reduction in display pixel size and independent scaling of memory cell size and display cell size.

Abstract: In one embodiment, the present invention includes a method of measuring a duration difference between a video frame and a corresponding modulation frame; and determining whether to change a duration of a future modulation frame based on the duration difference. The video frame and modulation frame may be part of a video stream and a modulation stream used to activate a display.

Abstract: In one embodiment, the present invention includes a method of driving a first display element with a first pixel waveform that is a function of a desired color for the first display element and a second waveform; and inserting an added transition into the first pixel waveform to maintain a bias between the first pixel waveform and the second waveform.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.

Abstract: A frame buffer for a microdisplay may be implemented with a repair algorithm that achieves desired uniformity in the frame buffer. Because the frame buffer and the display are tightly coupled, it is desirable to avoid providing unnecessary redundant elements which break up the uniformity of the overall integrated circuit. To this end, when a cell in the frame buffer is defective, a system to automatically address in its place an adjacent cell may be implemented. In one embodiment, control logic may address a column multiplexer to select an adjacent cell in an adjacent column in the same row to provide information in place of the defective cell in the frame buffer.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.

Abstract: A spatial light modulator may be adapted to receive bi-directional drive signals. The spatial light modulator may include a plurality of pixel elements having individual first electrodes and a common electrode providing a second electrode for each of the pixel elements. The pixel elements may be adapted to change between a first state and a second state in accordance with signals applied thereto, and the bi-directional drive signals may include at least a first drive signal and a second drive signal. Both drive signals are applied to change the pixel elements from the first state to the second state and from the second state to the first state.

Abstract: In a spatial light modulator, a frame may be broken up into a plurality of colors. A given frame may include at least a first portion and a second portion. During the first portion of the frame, more significant bits of the data for a given pixel may be displayed and during a second portion of the frame, less significant bits may be disclosed. In some embodiments, the frame may be broken into two color subframes for each color, but in other embodiments, more than two such subframes may be utilized. In one embodiment, the frame may be broken into red, blue, and green and each color may be displayed at least twice, such that more significant bits are displayed first and less significant bits are displayed thereafter.

Abstract: A light modulator such as an SLM, in which the pixel data array is decoupled from the pixel display array. The pixel data array can be located externally, permitting significant reduction in the circuitry present under each pixel of the display, in turn permitting significant reduction in display pixel size and independent scaling of memory cell size and display cell size.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device modified regions of a frame buffer. A frame buffer is divided into the regions, and data in the frame buffer represents pixels on the display device. The frame buffer accumulates writes until the region being written to changes, at which time the region is copied to the display device.

Abstract: In some embodiments, a display system includes a spatial light modulator including at least one pixel, a pixel source including pixel data corresponding to the pixel, a memory circuit connected to the pixel source and configured to store a pixel value corresponding to the pixel data, a pulse width modulation circuit connected between the memory circuit and the spatial light modulator, the pulse width modulation circuit adapted to generate a pulse to drive the pixel of the spatial light modulator, wherein a duration of the pulse corresponds to the pixel value and wherein the pulse is offset with respect to a start time and an end time of a refresh cycle of the spatial light modulator, and a control circuit connected to at least one of the memory circuit, the spatial light modulator, and the pulse width modulation circuit. Other embodiments are described and claimed.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which for example, may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Through use of the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.