Abstract: In a display refresh period, an array of display elements (e.g., pixels) forming a display device (e.g., a spatial light modulator) may be driven using selectively updated pulse width modulated waveforms. Decoupling of digital storage, storing display data that generates updated pulse width modulated waveforms, from the array of pixels may provide decoupling of pixel data and pulse width modulated waveform updates. In one embodiment, an update value of pixel data is provided to a display element. Using once the update value, a modulated signal may be generated for a display refresh period to drive the display element, significantly reducing updates required for the pixel data at the display element.

Abstract: In some embodiments, a display system includes a spatial light modulator including at least one pixel, a pixel source including pixel data corresponding to the pixel, a memory circuit connected to the pixel source and configured to store a pixel value corresponding to the pixel data, a pulse width modulation circuit connected between the memory circuit and the spatial light modulator, the pulse width modulation circuit adapted to generate a pulse to drive the pixel of the spatial light modulator, wherein a duration of the pulse corresponds to the pixel value and wherein the pulse is offset with respect to a start time and an end time of a refresh cycle of the spatial light modulator, and a control circuit connected to at least one of the memory circuit, the spatial light modulator, and the pulse width modulation circuit. Other embodiments are described and claimed.

Abstract: An array of display elements (e.g., pixels) in a display device (e.g., a spatial light modulator) may be digitally driven using pulse width modulated waveforms. Pulse width modulated waveforms may be locally generated to controllably drive each pixel in display systems with digital storage. A pixel drive circuit having a waveform generator may receive first digital data indicative of an optical output from an associated first display element. Moreover, second digital data indicative of a common reference with respect to a second display element may also be received at the first display element for comparison purposes. As a result, in one embodiment, a pulse width modulated waveform that includes only a single transition separating a first pulse interval and a second pulse interval may be generated based on a pixel value and a global count value instead of relying upon adding up multiple non-overlapping waveforms to drive a pixel.

Abstract: Pulse-width modulation may be utilized to drive one or more display elements of a display (e.g. pixels of a liquid crystal display system) comprising a controller that supplies digital information including global and local digital information to a respective signal generator associated with each display element operably coupled to the controller for receiving the digital information. In one embodiment, a spatial light modulator includes a respective local drive circuit associated with each pixel of a pixel array, and a global drive circuit operably coupled to the pixel array for digitally driving the pixel electrodes. Each local drive circuit may include a pixel logic, a digital storage, and pulse-width modulation circuitry. The global drive circuit may include a control logic, and a memory storing global digital information indicative of a common reference (e.g., a count value) and local digital information (e.g., a pixel value) indicative of an optical output from each pixel.

Abstract: A light modulator such as an SLM, in which the pixel data array is decoupled from the pixel display array. The pixel data array can be located externally, permitting significant reduction in the circuitry present under each pixel of the display, in turn permitting significant reduction in display pixel size and independent scaling of memory cell size and display cell size.

Abstract: A spatial light modulator having a double-buffering pixel value storage mechanism. A double-buffering mechanism enabling sparse refresh. A double-buffering value storage mechanism suitable for use with a serial or raster value producer and a value consumer, especially those in which it is desirable to consume an entire, completed frame or set of values at a time, and particularly those in which it is desirable to enable the producer to continue producing serially while the consumer is consuming in parallel fashion.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device modified regions of a frame buffer. A frame buffer is divided into the regions, and data in the frame buffer represents pixels on the display device. The frame buffer accumulates writes until the region being written to changes, at which time the region is copied to the display device.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.

Abstract: An multi-threading processor is provided. The multi-threading processor includes a front end module, an execution module coupled to the front end module, and a state module coupled to both the front end module and the execution module. The processor also includes a switch logic module, which is coupled to the state module. The switch logic module detects switching events and mispredicted branches and conceals switch latency by attempting to schedule switches to other software threads during the latencies of the mispredicted branches.

Abstract: A process for making a spinneret from a single body of metal with a yield strength of more than 350 MPa involving drilling lead spinneret holes into the mass of the body, annealing only a thin layer of the body opposite the lead holes, and forming capillary spinneret holes through the annealed layer to connect with the lead holes.

Abstract: A one-piece single metal spinneret is disclosed having a capillary zone with capillaries of a length more than 1.5 times the capillary diameter and a yield strength, outside the capillary zone, of greater than 350 MPa. A process for making the spinneret is, also, disclosed.