Abstract: A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.

Abstract: Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.

Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Abstract: Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.

Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.

Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.

Abstract: A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.

Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Abstract: By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.

Abstract: A method of forming a semiconductor structure includes providing a substrate having a first feature and a second feature. A mask is formed over the substrate. The mask covers the first feature. An ion implantation process is performed to introduce ions of a non-doping element into the second feature. The mask is adapted to absorb ions impinging on the first feature. After the ion implantation process, an annealing process is performed.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this way, a negative influence of the stress of metal silicide on the channel regions of field effect transistors may be significantly reduced, while nevertheless maintaining a low contact resistance.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.

Abstract: A method of forming the halo structures of a field effect transistor is disclosed. The halo structures are formed by implanting ions of a dopant material into the substrate on which the transistor is to be formed, wherein the tilt angle of the ion beam with respect to the surface of the substrate is varied according to a predefined time schedule comprising a plurality of implanting periods.