Abstract: In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.

Abstract: High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.

Abstract: By significantly suppressing or eliminating the channeling effects during implantation of a dopant species into the semiconductor region, the contribution of energy contamination may be studied and the corresponding results may be used in selecting appropriate tool settings for an actual implantation process. In this way, the vertical dopant profile may be controlled more precisely than in conventional processes. In one particular embodiment, the channeling effect is suppressed by an appropriately performed amorphization implantation process.

Abstract: By forming an implantation mask prior to the definition of the drain and the source areas, an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask, the lateral dimension of the gate electrode may be defined by well-established sidewall spacer techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.

Abstract: According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.

Abstract: An implanting process for amorphizing a crystalline substrate is proposed according to the present invention. In particular, according to the present invention, amorphous regions are formed in a substrate by exposing the substrate to an ion beam which is kept at a tilt angle between 10 and 80 degrees with respect to the surface of the substrate. Accordingly, ion channeling during subsequent implanting processes is prevented not only in the vertical direction but also in the horizontal direction so that doped regions exhibiting optimum doping profile tailoring may be realized.

Abstract: The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

Abstract: A cost-efficient and reliable method for assessing lateral dopant profiles includes the estimation of a reference profile formed below a gate structure of a transistor device. The overlap capacitance is then determined for at least two different overlaps, created by different spacer widths, and the lateral extension of a dopant profile to be measured, is estimated on the basis of a relationship between overlap capacitance and spacer width for the reference dopant profile.

Abstract: A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Abstract: The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.

Abstract: In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.

Abstract: A cost-efficient and reliable method for assessing lateral dopant profiles includes the estimation of a reference profile formed below a gate structure of a transistor device. The overlap capacitance is then determined for at least two different overlaps, created by different spacer widths, and the lateral extension of a dopant profile to be measured, is estimated on the basis of a relationship between overlap capacitance and spacer width for the reference dopant profile.

Abstract: An implanting process for amorphizing a crystalline substrate is proposed according to the present invention. In particular, according to the present invention, amorphous regions are formed in a substrate by exposing the substrate to an ion beam which is kept at a tilt angle between 10 and 80 degrees with respect to the surface of the substrate. Accordingly, ion channeling during subsequent implanting processes is prevented not only in the vertical direction but also in the horizontal direction so that doped regions exhibiting optimum doping profile tailoring may be realized.

Abstract: In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.

Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Abstract: The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.

Abstract: High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.

Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.

Abstract: A method of forming the halo structures of a field effect transistor is disclosed. The halo structures are formed by implanting ions of a dopant material into the substrate on which the transistor is to be formed, wherein the tilt angle of the ion beam with respect to the surface of the substrate is varied according to a predefined time schedule comprising a plurality of implanting periods.