Patents by Inventor Thomas G. Ference
Thomas G. Ference has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9074859Abstract: The present application is directed to a marking cartridge to be used with a hand tool. The marking cartridge comprises a support structure that includes an engaging element having an engaging end and enclosing surface, a positioning element parallel to the engaging element, the positioning element having a vertical positioning surface and lateral edges, and a vertical step connecting the engaging element to the positioning element to form a depressed support region. The cartridge further comprises an alignment lock extending from the engaging surface; a cartridge aliment guide extending from each lateral edge; a marking element having a marking surface, the marking element mounted in the depressed support region to the vertical positioning surface such that the marking surface extends beyond the enclosing surface; and a resilient material mounted in the depressed support region to the vertical positioning surface and extending beyond the marking surface.Type: GrantFiled: August 11, 2013Date of Patent: July 7, 2015Assignee: Anza CorporationInventors: Kathleen M. Dever, Thomas G. Ference
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Patent number: 7134933Abstract: A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.Type: GrantFiled: February 15, 2005Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Donald W. Brouillette, Thomas G. Ference, Harold G Linde, Michael S. Hibbs, Ronald L. Mendelson
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Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
Patent number: 6915795Abstract: A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.Type: GrantFiled: May 30, 2003Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Donald W. Brouillette, Robert F. Cook, Thomas G. Ference, Wayne J. Howell, Eric G. Liniger, Ronald L. Mendelson -
Patent number: 6887126Abstract: A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.Type: GrantFiled: December 7, 2001Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Donald W. Brouillette, Thomas G. Ference, Harold G. Linde, Michael S. Hibbs, Ronald L. Mendelson
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Patent number: 6838749Abstract: A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plane parallel to the surface of the substrate and a c-direction normal to the surface of the substrate. Generally, the method includes providing the substrate, growing the HTS film on the substrate and, after the HTS film has been grown, inducing into the HTS film a residual compressive strain the a-b plane and a residual tensile strain into the c-direction.Type: GrantFiled: October 6, 2003Date of Patent: January 4, 2005Assignee: Teracomm Research, inc.Inventors: Thomas G. Ference, Kenneth A. Puzey
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Patent number: 6813056Abstract: A short intense pulse of radiation is generated by shining radiation through a magneto-optical material and providing multiple stimulations to the material. The material is excited multiple times to rapidly change a property of the radiation, such as the angle of its polarization. The first excitation rotates the polarization in a first direction and the second excitation can rotate the polarization further. Alternatively the second excitation can bring the polarization back to its initial direction. Effect of lengthy relaxation times in the material cancel each other out and the pulse of light has a length that depends on the time difference between the two excitations and the spacing between them. This allows a pulse of light to be produced that has more rotation or has a shorter pulse width than the time for excitation plus the time for normal relaxation of the magneto-optical material.Type: GrantFiled: February 28, 2001Date of Patent: November 2, 2004Assignee: TeraComm Research inc.Inventors: William J. Cottrell, Thomas G. Ference, Kenneth A. Puzey
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Patent number: 6770501Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.Type: GrantFiled: October 23, 2002Date of Patent: August 3, 2004Assignee: International Business Machines CorporationInventors: Jay Burnham, Eduard A. Cartier, Thomas G. Ference, Steven W. Mittl, Anthony K. Stamper
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Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
Publication number: 20030211707Abstract: A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.Type: ApplicationFiled: May 30, 2003Publication date: November 13, 2003Inventors: Donald W. Brouillette, Robert F. Cook, Thomas G. Ference, Wayne J. Howell, Eric G. Liniger, Ronald L. Mendelson -
Patent number: 6630426Abstract: A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plane parallel to the surface of the substrate and a c-direction normal to the surface of the substrate. Generally, the method includes providing the substrate, growing the HTS film on the substrate and, after the HTS film has been grown, inducing into the HTS film a residual compressive strain the a-b plane and a residual tensile strain into the c-direction.Type: GrantFiled: November 16, 2000Date of Patent: October 7, 2003Assignee: TeraComm Research Inc.Inventors: Thomas G. Ference, Kenneth A. Puzey
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Patent number: 6611050Abstract: The present invention provides a method of forming a low profile chip interconnection, and the interconnection so formed. A recessed contact area is formed at an edge of the wafer. A conductive material is deposited within the adjacent contact areas of each recess, thereby electrically connecting the two chips. The recess may have substantially perpendicular sides, or sloped sides.Type: GrantFiled: March 30, 2000Date of Patent: August 26, 2003Assignee: International Business Machines CorporationInventors: Thomas G. Ference, Wayne J. Howell, William R. Tonti, Richard Q. Williams
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Patent number: 6600213Abstract: A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.Type: GrantFiled: May 15, 2001Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Donald W. Brouillette, Robert F. Cook, Thomas G. Ference, Wayne J. Howell, Eric G. Liniger, Ronald L. Mendelson
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Publication number: 20030102529Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.Type: ApplicationFiled: October 23, 2002Publication date: June 5, 2003Inventors: Jay Burnham, Eduard A. Cartier, Thomas G. Ference, Steven W. Mittl, Anthony K. Stamper
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Patent number: 6534389Abstract: A method for making electrical contacts to device regions in a semiconductor substrate, and the resulting structure, is presented. A first set of borderless contacts is initially formed. This first set of contacts is then contacted by a second series of smaller, upper-level contacts. The second set of contacts also contact the gate of the device. The structure which results has a form wherein there are stacked contacts to the diffusion layer, and a single level contact to the device gate. The structure further provides local interconnectability over gate structures.Type: GrantFiled: March 9, 2000Date of Patent: March 18, 2003Assignee: International Business Machines CorporationInventors: Thomas G. Ference, Kurt R. Kimmel, Alain Loiseau, Jed H. Rankin
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Patent number: 6521977Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.Type: GrantFiled: January 21, 2000Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Jay Burnham, Eduard A. Cartier, Thomas G. Ference, Steven W. Mittl, Anthony K. Stamper
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Patent number: 6517944Abstract: A multi-layer passivation barrier (24) for, and a method of, passivating a superconducting layer (22) of a microelectronic device (20). The passivation barrier includes a passivating layer (32) and a barrier buffering layer (30). The passivating layer provides a barrier to moisture, salts, alkali metals and the like located outside the device. The passivating layer also provides a barrier to outdiffusion of oxygen from the superconducting layer. The buffering layer permits oxygen to diffuse therethrough and provides a barrier to prevent diffusion of one or more constituent chemical elements of the passivating layer into the superconducting layer. The method includes the steps of depositing the barrier buffering layer (30) onto the superconducting layer (22) and depositing the passivating layer (32) onto the buffering layer.Type: GrantFiled: August 3, 2000Date of Patent: February 11, 2003Assignee: TeraComm Research Inc.Inventors: Kenneth A. Puzey, Thomas G. Ference
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Patent number: 6476956Abstract: A short pulse of radiation is generated by shining radiation through a magneto-optical material. The material is excited twice to rapidly change a property of the wave, such as the direction of the polarization. The first excitation rotates the polarization in a first direction and the second excitation brings the polarization back to its initial direction before the first excitation. Although the time for relaxation from the excitations may be lengthy, a pulse of light can be produced that is shorter in time than the time for excitation plus the time for relaxation. Light experiencing the pair of lengthy relaxations has each cancelling the effect of the other. The pulse of light has a length that depends on the time difference between the two excitations and the spacing between them. The rapid excitations are provided by pulses of current in a superconductor located near the magneto-optical material.Type: GrantFiled: February 28, 2001Date of Patent: November 5, 2002Assignee: TeraComm Research, Inc.Inventors: William J. Cottrell, Thomas G. Ference, Kenneth A. Puzey
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Publication number: 20020149830Abstract: A short pulse of radiation is generated by shining radiation through a magneto-optical material. The material is excited twice to rapidly change a property of the wave, such as the direction of the polarization. The first excitation rotates the polarization in a first direction and the second excitation brings the polarization back to its initial direction before the first excitation. Although the time for relaxation from the excitations may be lengthy, a pulse of light can be produced that is shorter in time than the time for excitation plus the time for relaxation. Light experiencing the pair of lengthy relaxations has each cancelling the effect of the other. The pulse of light has a length that depends on the time difference between the two excitations and the spacing between them. The rapid excitations are provided by pulses of current in a superconductor located near the magneto-optical material.Type: ApplicationFiled: February 28, 2001Publication date: October 17, 2002Inventors: William J. Cottrell, Thomas G. Ference, Kenneth A. Puzey
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Publication number: 20020118903Abstract: A short intense pulse of radiation is generated by shining radiation through a magneto-optical material and providing multiple stimulations to the material. The material is excited multiple times to rapidly change a property of the radiation, such as the angle of its polarization. The first excitation rotates the polarization in a first direction and the second excitation can rotate the polarization further. Alternatively the second excitation can bring the polarization back to its initial direction. Effect of lengthy relaxation times in the material cancel each other out and the pulse of light has a length that depends on the time difference between the two excitations and the spacing between them. This allows a pulse of light to be produced that has more rotation or has a shorter pulse width than the time for excitation plus the time for normal relaxation of the magneto-optical material.Type: ApplicationFiled: February 28, 2001Publication date: August 29, 2002Inventors: William J. Cottrell, Thomas G. Ference, Kenneth A. Puzey
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Publication number: 20020113324Abstract: A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.Type: ApplicationFiled: April 24, 2002Publication date: August 22, 2002Applicant: International Business Machines CorporationInventors: Steven A. Cordes, Peter A. Gruber, James L. Speidell, Wayne J. Howell, Thomas G. Ference
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Patent number: 6429958Abstract: The optical assembly for modulating input light and providing modulated light at an output thereof includes a first arrangement, which includes a layer of a superconductive material having at least a part of the input light incident thereon as incident light. The superconductive material is switchable between a first state, in which the superconductive material exhibits a first refractive index, and a second state, in which the superconductive material exhibits a second refractive index. The first arrangement is configured to direct to the output as the modulated light a first fraction of the incident light, when the superconductive material is in the first state, and a second fraction of the incident light, when the superconductive material is in the second state, such that the modulated light exhibits a given value of extinction ratio, which is defined as a ratio of the first fraction of the incident light to the second fraction of the incident light at the output.Type: GrantFiled: March 22, 2001Date of Patent: August 6, 2002Assignee: TeraComm Research, Inc.Inventors: Kenneth A. Puzey, William J. Cottrell, Thomas G. Ference