Abstract: A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

Abstract: A semiconductor structure including a first substrate and a second substrate joined to the first substrate. A plurality of contacts extend between the first substrate and the second substrate. A plurality of first solder bumps are connected between the first substrate and the second substrate for aligning the contacts.

Abstract: A semiconductor device having borderless contacts thereby providing a device having a reduced overall size. In particular, the device includes a plurality of shallow trench isolations and a plurality of dielectric isolations thereon to separate the adjoining device components and prevent shorts. Sidewall spacers surrounding and extend slightly above the device gates and dielectric isolations to further prevent shorts. A layer of conductive material atop each gate and diffusion region provides for coplanar contact surfaces. A layer of silicide beneath select regions of the conductive layer enhance electrical conductivity within the device. An internal wireless interconnection to electrically connect diffusion regions of different logic devices within the structure is also provided.

Abstract: A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

Abstract: A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

Abstract: A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

Abstract: A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

Abstract: An apparatus for simultaneously removing heat from two surfaces of a semiconductor structure includes a heat sink mounted to a front surface and a heat sink mounted to a back surface of the semiconductor structure. The structure can be two chips mounted in face-to-face arrangement, and the heat sinks remove heat from back surfaces of both chips.

Abstract: A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.

Abstract: A semiconductor structure includes a stack of two semiconductor chips. An edge of the chips forms a side surface of the stack. Insulation and adhesive is located between the chips, and a wire contacting circuitry on one of the chips extends through the insulation to the side surface. A first conductor contacts the wire on the side surface. The first conductor is self-aligned to the wire and extends above the side surface. The first conductor facilitates pads or connectors on the side surface that are insulated from the semiconductor chips. The self-aligned first conductor is an electroplated or electroless plated metal.

Abstract: Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

Abstract: This discloses a probe structure which does not rely on cantilevered wire and which has improved and controlled contact pressure between the probe tip contacts and the I/O pads on a semiconductor chip and which comprises a plurality of conductive contact electrodes, electrically coupled to respective leads, formed on a film stretched across a respective plurality of through holes established in a substrate. The through holes and the contact electrodes are aligned with one another and both positionally match selected I/O pads existing on a semiconductor chip to be probed. Also disclosed is a probe utilizing means connected to each one of the holes to control the pressure in the holes and between the probes and any contact on a device in contact with the probe.

Abstract: A semiconductor structure includes a stack of two semiconductor chips. An edge of the chips forms a side surface of the stack. Insulation and adhesive is located between the chips, and a wire contacting circuitry on one of the chips extends through the insulation to the side surface. A first conductor contacts the wire on the side surface. The first conductor is self-aligned to the wire and extends above the side surface. The first conductor facilitates pads or connectors on the side surface that are insulated from the semiconductor chips. The self-aligned first conductor is an electroplated or electroless plated metal.

Abstract: A semi-conductor device having a conductive lead with an exposed tip disposed within a first insulative material, which is in turn disposed between insulated first and second integrated circuit chips is disclosed. The first insulative material is etched to form a recess after which a second insulative material is deposited on the access plane of the chips and within the recess. The tip of the wire lead is then exposed by either a chemical mechanical polish or by a wet etch/develop process.

Abstract: A semi-conductor device having a conductive lead with an exposed tip disposed within a first insulative material, which is in turn disposed between insulated first and second integrated circuit chips is disclosed. The first insulative material is etched to form a recess after which a second insulative material is deposited on the access plane of the chips and within the recess. The tip of the wire lead is then exposed by either a chemical mechanical polish or by a wet etch/develop process.

Abstract: An apparatus and method are described for injection molding solder mounds onto electronic devices. The apparatus has a reservoir for molten solder which is disposed over a cavity in an injection plate. The injection plate is disposed over a mold having an array of cavities therein into which solder in injection molded. The mold is disposed over a workpiece, such as a semiconductor chip or a semiconductor chip packaging substrate. The cavities in the mold are aligned with electrical contact locations on the chip or substrate. The workpiece is heated and the molten solder is forced under gas pressure into the cavity in the injection plate disposed above the array of cavities in the mold. The molten solder is forced into the array of cavities in the mold. The injection plate is advanced to slide over the mold to wipe away the excess solder above the mold at a plurality of wiping apertures in the injection plate.