Patents by Inventor Thomas Gregg

Thomas Gregg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8656375
    Abstract: A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rajaram B. Krishnamurthy, Thomas A. Gregg
  • Patent number: 8656228
    Abstract: A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Check, David F. Craddock, Thomas A. Gregg, Pak-kin Mak, Gary E. Strait
  • Patent number: 8650335
    Abstract: A measurement facility is provided for capturing and presenting fine-grained usage information for adapter functions in an input/output subsystem. Adapter specific input/output traffic is tracked on a per function basis and the results are dynamically presented to the user. This information is useful for performance tuning, load balancing and usage based charging, as examples.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Frank W. Brice, Jr., David Craddock, Beth A. Glendening, Thomas A. Gregg, Eric N. Lais, Peter K. Szwed, Steven G. Wilkins
  • Patent number: 8650337
    Abstract: Various address translation formats are available for use in obtaining system memory addresses for use by requestors in accessing system memory. The particular address translation format to be used by a given requestor, an example of which is an adapter function, is pre-registered in a device table entry associated with that requestor.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais, Donald W. Schmidt
  • Patent number: 8645606
    Abstract: Embodiments of the invention relate to upbound input/output expansion requests and response processing in a PCIE architecture. A first request to perform an operation on a host system is intitiated. The first request is formatted for the first protocol and includes data that is required in order to process the first request. A second request is created in response to the first request, the second request includes a header and is formatted according to the second protocol. The data required to process the first request in the header of the second request is stored, and the second request is sent to the host system.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, David F. Craddock, Eric N. Lais
  • Patent number: 8645767
    Abstract: Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An error is detected in a communication initiated between a function and the system memory, the communication including an I/O request from an application. Future communication between the function and the system memory is prevented in response to the detecting. The application is notified that the error in communication occurred in response to the detecting.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
  • Patent number: 8639858
    Abstract: Address spaces are resized concurrent to accessing those address spaces. The size of an address space can be increased or decreased concurrent to performing read or write operations on the address space. Further, cache entries associated with an address space being decreased in size are purged.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Donald W. Schmidt
  • Patent number: 8635430
    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
  • Patent number: 8631222
    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
  • Patent number: 8626970
    Abstract: Access to an input/output adapter by a configuration is controlled. For each requested access to an adapter, checks are made to determine whether the configuration is authorized to access the adapter. If it is not authorized, then access is denied. If it is authorized, but access should be temporarily blocked, then instruction execution is altered to indicate such. If access is permitted, but should be blocked for another reason (other than temporarily), then access is denied.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner
  • Patent number: 8621112
    Abstract: A tiered discovery capability is employed to obtain attributes regarding adapters of an I/O configuration. The first tier obtains a list of the adapter functions accessible to an operating system; the second tier obtains attributes regarding a selected adapter function of the list of adapter functions; and a third tier obtains common attributes of a group of adapter functions, the group including the selected adapter function.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony F. Coneski, David Craddock, Charles W. Gainey, Jr., Beth A. Glendening, Thomas A. Gregg, Ugochukwu C. Njoku
  • Patent number: 8615622
    Abstract: A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Gerd K. Bayer, David F. Craddock, Michael Jung, Eric N. Lais, Elke G. Nass
  • Patent number: 8615645
    Abstract: An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner, Gustav E. Sittmann, III, Peter K. Szwed
  • Patent number: 8601497
    Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Janet R. Easton, Mark S. Farrell, Thomas A. Gregg, Eric N. Lais, Cynthia Sittmann
  • Patent number: 8589603
    Abstract: A request to perform an operation, such as a remote direct memory access (RDMA) write operation or a send operation that writes to memory, is sent from a sending input/output (I/O) adapter (e.g., an RDMA-capable adapter) to a receiving I/O adapter. The receiving I/O adapter receives the request and initiates performance of the operation, but delays sending an acknowledgment for the operation. The acknowledgment is delayed until the operation is complete (i.e., until the memory is updated and the data is visible to the remote processor), as determined by a read operation initiated and performed by the receiving I/O adapter transparent to the sending I/O adapter.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Thomas A. Gregg
  • Patent number: 8572635
    Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Janet R. Easton, Mark S. Farrell, Thomas A. Gregg, Eric N. Lais, Gustav E. Sittmann, III
  • Patent number: 8566480
    Abstract: Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Mark S. Farrell, Thomas A. Gregg, Dan F. Greiner
  • Patent number: 8549182
    Abstract: Communication with adapters of a computing environment is facilitated. Control instructions specifically designed for communicating data to and from adapters are provided to facilitate the communication. The instructions explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter, such as a Peripheral Component Interconnect (PCI) or Peripheral Component Interconnect Express (PCIe) adapter.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Mark S. Farrell, Thomas A. Gregg, Dan F. Greiner
  • Patent number: 8547845
    Abstract: Detecting and recovering from soft errors in a network comprising a first device. A first device receives a first data packet. Responsive to receiving a second data packet, the first device determines whether the two data packets are identical. Responsive to the determination that the two data packets are not identical, the first device discards the two data packets, and requests retransmission of the two data packets.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Casimer M DeCusatis, Thomas A Gregg, Rajaram B Krishnamurthy, Anuradha Rao
  • Patent number: 8542597
    Abstract: Detecting and recovering from soft errors in a network comprising a first device. A first device receives a first data packet. Responsive to receiving a second data packet, the first device determines whether the two data packets are identical. Responsive to the determination that the two data packets are not identical, the first device discards the two data packets, and requests retransmission of the two data packets.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Casimer M DeCusatis, Thomas A Gregg, Rajaram B Krishnamurthy, Aburadha Rao