Patents by Inventor Thomas Gregg

Thomas Gregg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110131430
    Abstract: Accelerators of a computing environment are managed in order to optimize energy consumption of the accelerators. To facilitate the management, virtual queues are assigned to the accelerators, and a management technique is used to enqueue specific tasks on the queues for execution by the corresponding accelerators. The management technique considers various factors in determining which tasks to be placed on which virtual queues in order to manage energy consumption of the accelerators.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajaram B. Krishnamurthy, Thomas A. Gregg
  • Patent number: 7952998
    Abstract: An Infiniband flow control scheme disables credit based flow control so that transmission distances can be extended. An Infiniband credit based flow control suffers from round trip time lag that slows transmission rates. Disabling Infiniband credit based flow control enables back to back packet transmission because credit counts are ignored. Nonetheless, packets can be lost due to overruns in a receive buffer, therefore, packet drop detection mechanisms are employed so that the Infiniband receiver can send requests to the Infiniband transmitter to temporarily slow its Infiniband transmission rate.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, David Craddock
  • Publication number: 20110107035
    Abstract: A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajaram B. Krishnamurthy, Thomas A. Gregg
  • Publication number: 20110107066
    Abstract: Accelerator functions are cascaded, such that a result of one accelerator function is directly forwarded to another accelerator function, bypassing the processor requesting the functions to be performed. The cascading may be provided during compilation of a program specifying the functions to be performed, but can be dynamically reversed during runtime of the program.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajaram B. Krishnamurthy, Thomas A. Gregg
  • Publication number: 20110068957
    Abstract: A system to compress an inter-system channel data stream may include a data compression application executing via a computer processor. The system may additionally include a transmit dictionary used by said data compression application to compress an inter-system channel data stream. The system may also include a data decompression application executing via a second computer processor to decompress the inter-system channel data stream. The system may further include a receive dictionary used by said data decompression application to decompress the inter-system channel data stream.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg
  • Patent number: 7899050
    Abstract: A low latency multicasting receive and send apparatus and method comprising low latency receive and send queues. In an InfiniBand® network each destination group of nodes (recipients) is identified by a unique Global ID (GID)+Local ID (LID). Each node whose ports are part of a multicast group identify themselves via a LID which identifies participating ports. When a switch receives such a multicast packet with a multicast LID in the packet's DLID field it replicates the packet to each of the designated ports. Each destination adapter at a receiving node receives the multicast packet and distributes copies of the packet to QPs in the host system that are registered for the multicast address.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Thomas A. Gregg
  • Patent number: 7895383
    Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Richard L. Arndt, Bruce L. Beukema, David Craddock, Ronald E. Fuhs, Steven L. Rogers, Donald W. Schmidt, Bruce M. Walk
  • Patent number: 7886306
    Abstract: A system and process for passing messages directly between instances of Operating System (OSs) and plurality of Coupling Facilities (CFs) through Sharable InterSystem Channels (ISCs) and without polling, in one or more Computer Electronic Complexes (CECs). Primary messages and associated secondary messages are passed by a hypervisor using a hypervisor memory.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Patent number: 7876751
    Abstract: Communication over a computer network with a node having a first port with a point-to-point link connection to a second node having a second port. The first port transmits to the second port a reliable link layer (RLL) packet over the link. The RLL packet comprises a first RLL header and a first data packet, the first RLL header preceding the first data packet, the first RLL header comprising an RLL start-of-frame (SOF) character and an RLL packet sequence number (PSN). If the first port receives an RLL acknowledgment control packet from the link, it acknowledges receipt of the first data packet, and the first port does not retain the first data packet in the buffer. If the first port does not receive the RLL acknowledgment packet from the link, acknowledging receipt of the first data packet, the first port re-transmits from the buffer the first data packet.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alan F. Benner, David Craddock, Thomas A. Gregg
  • Patent number: 7865668
    Abstract: A method, system, and computer program product for two-sided, dynamic cache injection control are provided. An I/O adapter generates an I/O transaction in response to receiving a request for the transaction. The transaction includes an ID field and a requested address. The adapter looks up the address in a cache translation table stored thereon, which includes mappings between addresses and corresponding address space identifiers (ASIDs). The adapter enters an ASID in the ID field when the requested address is present in the cache translation table. IDs corresponding to device identifiers, address ranges and pattern strings may also be entered. The adapter sends the transaction to one of an I/O hub and system chipset, which in turn, looks up the ASID in a table stored thereon and injects the requested address and corresponding data in a processor complex when the ASID is present in the table, indicating that the address space corresponding to the ASID is actively running on a processor in the complex.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Rajaram B. Krishnamurthy
  • Publication number: 20100306442
    Abstract: An article of manufacture, an apparatus, and a method for processing packets in a peripheral component interconnect express (PCIe) network. An article of manufacture includes a computer program product that includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a PCIe posted write packet at a receiving device, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device. An expected tag identifier is determined for the requesting device. The received tag identifier is compared to the expected tag identifier. An error flag is set if the received tag identifier does not match the expected tag identifier.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 2, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Thomas A. Gregg
  • Patent number: 7839777
    Abstract: The response time for resolving network traffic congestion is accelerated in a Data Center Ethernet (DCE) network. A data packet is received at a node in the network. Congestion of the data packet at the node is detected, and a backward congestion notification signal for the data packet is generated. A packet injection rate is adapted based on at least one of the backward congestion notification signal generated by the node and another backward congestion notification signal.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Casimer DeCusatis, Thomas A. Gregg
  • Patent number: 7836254
    Abstract: A method, system, and computer program product for cache injection using speculation are provided. The method includes creating a cache line indirection table at an input/output (I/O) hub, which includes fields and entries for addresses, processor ID, and cache type and includes cache level line limit fields. The method also includes setting cache line limits to the CLL fields and receiving a stream of contiguous addresses at the table. For each address in the stream, the method includes: looking up the address in the table; if the address is present in the table, inject the cache line corresponding to the address in the processor complex; if the address is not present in the table, search limit values from the lowest level cache to the highest level cache; and inject addresses not present in the table to the cache hierarchy of the processor last injected from the contiguous address stream.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Rajaram B. Krishnamurthy
  • Patent number: 7836255
    Abstract: A method and system for cache injection using clustering are provided. The method includes receiving an input/output (I/O) transaction at an input/output device that includes a system chipset or input/output (I/O) hub. The I/O transaction includes an address. The method also includes looking up the address in a cache block indirection table. The cache block indirection table includes fields and entries for addresses and cluster identifiers (IDs). In response to a match resulting from the lookup, the method includes multicasting an injection operation to processor units identified by the cluster ID.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Rajaram B. Krishnamurthy
  • Patent number: 7826745
    Abstract: A method and apparatus for transmitting signals from a plurality of input channels over a TDM optical network, where each of the input channels contains an optical data signal and an electrical control signal containing control information relating to the optical data signal. In accordance with the invention, respective optical receivers convert the optical data signals to respective electrical data signals, which a TDM data multiplexer time-multiplexes to generate a multiplexed data signal. A TDM control signal multiplexer time-multiplexes the electrical control signals to generate a multiplexed control signal that is combined with said multiplexed data signal to generate a composite electrical signal. An optical transmitter generates a composite optical signal from the composite electrical signal that is transmitted over the network, optionally after WDM multiplexing it with other composite optical signals.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg
  • Patent number: 7821939
    Abstract: Congestion is adaptively controlled in a data center Ethernet (DCE) network. Packets are received over at least one virtual lane in the DCE network. An absolute or relative packet arrival rate is computed over a time period. The absolute or relative packet arrival rate is compared to at least a first threshold and a second threshold. If the absolute or relative packet arrival rate increases beyond the first threshold, the packet transmission rate is caused to decrease. If the absolute or relative packet arrival rate is less than a second threshold, the packet transmission rate is caused to increase.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Casimer DeCusatis, Thomas A. Gregg
  • Patent number: 7809869
    Abstract: Methods, systems, and apparatus are disclosed for throttling a point-to-point, serial I/O expansion subsystem within a computing system that include: receiving, by a link configuration module, an external environmental parameter value representing a condition of an environment external to the computing system; determining, by the link configuration module, a link configuration of a communication link for an I/O adapter in a point-to-point, serial I/O expansion subsystem within the computing system in dependence upon the external environmental parameter value; and configuring, by the link configuration module, the communication link for the I/O adapter in dependence upon the link configuration.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: William E. Atherton, Thomas A. Gregg, Paul J. Mattos
  • Patent number: 7796642
    Abstract: A system and a method for initializing a communication link for transmitting a data stream from a first computer through a synchronous optical communication network to a second computer are provided. The method includes transmitting a first request message in a first GFP data frame to a second computer. The method further includes transmitting a second acknowledgement message in a second GFP data frame from the second computer to the first computer. The method further includes initializing the communication link between the first computer and the second computer in response to the acknowledgement message.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: September 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Casimer Maurice DeCusatis, Thomas A. Gregg
  • Patent number: 7787765
    Abstract: A method and apparatus for initializing an end-to-end link in a fiber optic communications system in which a pair of nodes interconnect a pair of end devices. A first node, upon initializing a device link segment with an end device to which the node is coupled, sends a signal to the other node over a network link segment indicating that the sending node has initialized its device link segment. The first node completes initialization of the end-to-end link upon receiving a signal from the other node over the network link segment indicating that the other node has initialized its device link segment. In an alternative initialization scheme, a node momentarily operates its data channel in a loopback mode to allow its end device to initialize the device link segment in accordance with a predetermined protocol before returning to a transparent mode.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Thomas A. Gregg
  • Patent number: 7710990
    Abstract: A receive queue provided in a computer system holds work completion information and message data together. An InfiniBand hardware adapter sends a single CQE+message data to the computer system that includes the completion information and data. This information is sufficient for the computer system to receive and process the data message, thereby providing a highly scalable low latency receiving mechanism.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Thomas A. Gregg, Thomas Schlipf