Abstract: Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

Abstract: Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.

Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

Abstract: Techniques are provided for reducing power consumption in memory cells. A static (SRAM) memory cell includes two cross coupled inverters. One or more transistors are coupled between the inverters and the power supply voltages. The transistors are turned OFF for a period of time during a memory state transition to block current flow between the high power supply voltage and the low power supply voltage to reduce power consumption.

Abstract: Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

Abstract: A programmable logic device includes a memory with user selectable power consumption. During configuration, the memory operates at a relatively high power consumption level and quickly outputs configuration information. During normal operation, the memory selectively operates at the high power level or at a lower power level. The lower power level provides a lower rate of memory access than the high power level. The lower power level may be selected when the user desires to power other areas of the programmable logic device or when the user desires a lower rate of memory access. In this manner, a single memory can serve multiple functions without consuming an excessive amount of power.

Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

Abstract: The present invention broadly provides an improved ingestible capsule (28) that is arranged to sense one or more physiological parameters within a mammalian body, an to transmit such parameters to an extra-corporeal receiver (50). In use, the capsule and receiver perform the method of determining the real-time location of the capsule within a tract of a mammal. This method includes the steps of providing the capsule, the capsule having one or more sensors, ingesting the capsule, transmitting a signal from the capsule, receiving the transmitted signal, and determining the real-time location of the capsule within the tract as a function of the received signal. The received signal may also indicate the value of one or more sensed parameters.

Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal; levels, including low supply signal levels, while limiting leakage current effects.

Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

Abstract: An integrated circuit has one or more external control pins to control and indicate which of two or more different VCC or other voltage levels will be used. The control pin receives a logic signal, high or low, and draws zero static power. A user can use the integrated circuit with two or more VCC voltage levels by indicating which voltage level at the control pins. In a specific embodiment, the integrated circuit has nonvolatile memory cells such as EEPROM or Flash cells that a configurable and reconfigurable using on-chip programming circuitry. The programming circuitry may generate and use superhigh or high voltages, higher than the VCC voltage.

Abstract: A bicycle seat assembly having a functional surface area comprising a main support surface region and a center tactile surface region. At the center tactile surface region there is a raised center surface portion and outwardly facing side tactile surface portions to engage upper rear and side thigh surface portions of the person. There are right and left and primary support zones spaced on opposite sides of the longitudinal axis to support the right and left ischial-tuberosities of the person who is in a seated pedaling position. The forward support surface portions on opposite sides of the center tactile surface region are contoured so that the leading edge thereof has an upward and rearward slope. The seat is arranged to accommodate 95% of the adult population in the U.S., enables the cyclist to operate effectively in the seated pedaling, the seated non-pedaling mode and the stand-up pedaling mode.

Abstract: A method of preventing clogging and leaking in an automobile air vent system where there is an upwardly facing air vent grill which is made of a magnetically permeable material and is positioned at an upper portion of the body surface of the automobile forwardly of the windshield. This air vent is covered by a generally planar intake cover having a perimeter configuration substantially the same as the vent intake opening. This cover is made of a magnetic material which when placed over the vent cover remains securely in place and prevents the clogging (and thus leaking) of the air vent system.

Abstract: A bicycle seat assembly having a functional surface area comprising a main support surface region and a center tactile surface region. At the center tactile surface region there is a raised center surface portion and outwardly facing side tactile surface portions to engage upper rear and side thigh surface portions of the person. There are right and left and primary support zones spaced on opposite sides of the longitudinal axis to support the right and left ischial-tuberosities of the person who is in a seated pedaling position. The forward support surface portions on opposite sides of the center tactile surface region are contoured so that the leading edge thereof has an upward and rearward slope. The seat is arranged to accommodate 95% of the adult population in the U.S., and enables the cyclist to operate effectively in the seated pedaling mode, the seated non-pedaling mode and the stand-up pedaling mode.

Abstract: Various embodiments for improved I/O pin pull-up circuitry are disclosed. The pull-up devices according to the present invention minimize dissipation of crowbar current when the I/O pin is tri-stated. Circuit techniques are disclosed for minimizing the crowbar current as well as making the circuit high voltage tolerant.

Abstract: A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.

Abstract: Disclosed is an integrated circuit design and method which provides optional configurations depending upon the connection of optional bond wires. The design retains the flexibility of the IC's mode of operation through the fabrication and testing of the wafers, until the packaging of the IC. ICs designed in accordance with the present inventions also provide advantages of size, efficiency and reliability over those previously known.