Abstract: An integrated circuit chip includes an output node, receiver front ends, and control logic. The receiver front ends are configured to receive an input signal. Each of the receiver front ends is configured to receive the input signal and provide an output signal at the output node. At least one of the receiver front ends is configured to selectively consume less power. The control logic is configured to select the number of receiver front ends providing an output signal to the output node based on a received signal strength indication.

Abstract: A system including an output node and receiver front ends. The receiver front ends are configured to receive an input signal. Each of the receiver front ends is configured to receive the input signal and provide an output signal at the output node. At least one of the receiver front ends is configured to selectively consume less power.

Abstract: A system including an output node and receiver front ends. The receiver front ends are configured to receive an input signal. Each of the receiver front ends is configured to receive the input signal and provide an output signal at the output node. At least one of the receiver front ends is configured to selectively consume less power.

Abstract: A device for detecting a measured quantity has a sensor chip for detecting the measured quantity, a supply for providing a power supply, and an injection-molded enclosure for accommodating the sensor chip and the supply, the injection-molded enclosure including integrated conductive traces providing an electrical connection between the sensor chip and the supply.

Abstract: A device and associated method for passing parameters to a finger in a rake receiver are disclosed. The finger is initially operated with a first parameter set which is held in a first memory area (PAR_RAM). To change the parameter set, a second parameter set is loaded into a second memory area (PAR_CHG_RAM1/2), a check is carried out to determine whether a switching condition (SCHED_RAM) is satisfied, and if it is an access for that finger is switched (MUX) from the first memory area (PAR_RAM) to the second memory area.

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.

Abstract: A device for detecting a measured quantity has a sensor chip for detecting the measured quantity, a supply for providing a power supply, and an injection-molded enclosure for accommodating the sensor chip and the supply, the injection-molded enclosure including integrated conductive traces providing an electrical connection between the sensor chip and the supply.

Abstract: A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.

Abstract: A device and associated method for passing parameters to a finger in a rake receiver are disclosed. The finger is initially operated with a first parameter set which is held in a first memory area (PAR_RAM). To change the parameter set, a second parameter set is loaded into a second memory area (PAR_CHG_RAM1/2), a check is carried out to determine whether a switching condition (SCHED_RAM) is satisfied, and if it is an access for that finger is switched (MUX) from the first memory area (PAR_RAM) to the second memory area.

Abstract: A combined interleaving and deinterleaving circuit (IDL1) has a first data memory (RAM) for temporary storage of the data to be interleaved and deinterleaved. A first address generator produces a sequence of sequential addresses, and a second address generator (AG) produces a sequence of addresses which represents the interleaving rule (?(i)). A logic means (XOR, MUX) causes the data memory (RAM) to be addressed by the second address generator (AG) in the interleaving mode for a read process and in the deinterleaving mode for a write process.

Abstract: A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.