Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A computer system having a host adapter is provided. The host adapter includes a primary port that follows a primary communication protocol. The primary port is connectable to at least one peripheral device. The host adapter includes a service port that follows a service communication protocol to monitor and send recovery commands to the peripheral device. The service port is decoupled and separate from the primary port and connectable to the at least one peripheral device.

Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.

Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.

Abstract: A computer system having a host adapter is provided. The host adapter includes a primary port that follows a primary communication protocol. The primary port is connectable to at least one peripheral device. The host adapter includes a service port that follows a service communication protocol to monitor and send recovery commands to the peripheral device. The service port is decoupled and separate from the primary port and connectable to the at least one peripheral device.

Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.

Abstract: Embodiments relate to optimizing write performance of a flash device. Aspects include receiving a request to evict a plurality of pages from a main memory and determining a block size for the flash device. Aspects also include grouping the plurality of pages from the main memory into a move specification block, wherein a size of the move specification block is the block size and writing the move specification block to the flash device. The block size being determined based on one or more operational characteristics of the flash device.

Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.

Abstract: The present invention relates to immunogenic compositions containing an antigen of interest entrapped with a crosslinked carrier protein matrix, methods of making such vaccines, and methods of vaccine administration, wherein the immunogenicity of the protein matrix, and hence its effectiveness as a vaccine, is improved by controlling or selecting the particle size of the protein matrix particles to eliminate low molecular weight particles, e.g., less than 100 nm in diameter.

Abstract: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

Abstract: Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.

Abstract: A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register.

Abstract: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.