Patents by Inventor Thomas J. Miller

Thomas J. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6583450
    Abstract: A II-VI semiconductor device includes a stack of II-VI semiconductor layers electrically connected to a top electrical contact. A GaAs substrate is provided which supports the stack of II-VI semiconductor layers and is positioned opposite to the top electrical contacts. A BeTe buffer layer is provided between the GaAs substrate and the stack of II-VI semiconductor layers. The BeTe buffer layer reduces stacking fault defects at the interface between the GaAs substrate and the stack of II-VI semiconductor layers.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: June 24, 2003
    Assignee: 3M Innovative Properties Company
    Inventor: Thomas J. Miller
  • Publication number: 20030080697
    Abstract: A hand-held fluorescent lamp assembly powered by typical line supply of 120 VAC, 60 Hz via an attached power cord and employing multiple commonly available fluorescent lamps. The assembly includes switches to independently control the multiple fluorescent lamps. The assembly includes lightweight solid state power regulation components. The power regulation circuit employs a self-oscillating circuit that is approximately matched in frequency of oscillation to the natural frequency of the fluorescent lamp load to automatically ignite the fluorescent lamps. The power regulation circuit includes circuit elements to automatically protect the ballast circuit and lamps from overdrawing in the run state and from abnormal load conditions.
    Type: Application
    Filed: December 10, 2002
    Publication date: May 1, 2003
    Inventors: Thomas J. Miller, Zhou Dong Yue
  • Patent number: 6534926
    Abstract: A hand-held fluorescent lamp assembly powered by typical line supply of 120 VAC, 60 Hz via an attached power cord and employing multiple commonly available fluorescent lamps. The assembly includes switches to independently control the multiple fluorescent lamps. The assembly includes lightweight solid state power regulation components. The power regulation circuit employs a self-oscillating circuit that is approximately matched in frequency of oscillation to the natural frequency of the fluorescent lamp load to automatically ignite the fluorescent lamps. The power regulation circuit includes circuit elements to automatically protect the ballast circuit and lamps from overdrawing in the run state and from abnormal load conditions.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: March 18, 2003
    Assignee: TMC Enterprises, a division of Tasco Industries, Inc.
    Inventors: Thomas J. Miller, Zhou Dong Yue
  • Publication number: 20020141561
    Abstract: A method and system schedules inbound inquiries, such as inbound telephone calls, for response by agents in an order that is based in part on the forecasted outcome of the inbound inquiries. A scheduling module applies inquiry information to a model to forecast the outcome of an inbound inquiry. The forecasted outcome is used to set a priority value for ordering the inquiry. The priority value may be determined by solving a constrained optimization problem that seeks to maximize an objective function, such as maximizing an agent's productivity to produce sales or to minimize inbound call attrition. A modeling module generates models that forecast inquiry outcomes based on a history and inquiry information. Statistical analysis such as regression analysis determines the model with the outcome related to the nature of the inquiry. Operator wait time is regulated by forcing low priority and/or highly tolerant inbound inquiries to self service.
    Type: Application
    Filed: February 25, 2002
    Publication date: October 3, 2002
    Applicant: Austin Logistics Incorporated
    Inventors: Daniel N. Duncan, Alexander N. Svoronos, Thomas J. Miller
  • Patent number: 6439360
    Abstract: An extension cord reel assembly having a housing which has a spool portion and a mounting portion is provided. A spool member having at least one flange member that is continuously welded to a surface upon which the extension cord is to be stored is positioned within the spool portion of the housing. The mounting portion of the housing of the reel assembly is positioned adjacent an outer perimeter of the spool member and is adapted to attach to a suspension member from which the reel assembly can be suspended above the ground.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: August 27, 2002
    Assignee: TMC Enterprises, a divison of Tasco Industries, Inc.
    Inventor: Thomas J. Miller
  • Patent number: 6376273
    Abstract: A II-VI semiconductor device includes a stack of semiconductor layers. An ohmic contact is provided that electrically couples to the stack. The ohmic contact has an oxidation rate when exposed to an oxidizing substance. A passivation capping layer overlies the ohmic contact and has an oxidation rate that is less than the oxidation rate of the ohmic contact.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: April 23, 2002
    Assignee: 3M Innovative Properties Company
    Inventors: Fen-Ren Chien, Michael A. Haase, Thomas J. Miller
  • Patent number: 6302701
    Abstract: A sub-miniature push-on RF connector for connecting a transmission line to a signal sink. The connector has a shielded transmission line section having a signal line and a ground line extending axially through the connector. A center pin is coupled to the signal line and extends from the center of a front face of the connector in an axial direction. A semicircular tab coupled to the ground line extends from the front face of the connector substantially along the length of the center pin and partially surrounding the center pin to reduce an air gap impedance, the tab having first and second wire bonding surfaces at the ends of the semicircular shape thereof and disposed adjacent to said center pin.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: October 16, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Thomas J. Miller, Jr., Yuan-Hua Kao, Bettina A. Nechay, Hidenori Nakanishi, Takashi Igarashi, Motoyoshi Tanaka
  • Patent number: 6249866
    Abstract: A system and method for encryption and decryption of files. The system and method operate in conjunction with the file system to transparently encrypt and decrypt files in using a public key-private key pair encryption scheme. When a user puts a file in an encrypted directory or encrypts a file, all data writes to the disk for that file are encrypted with a random file encryption key generated from a random number and encrypted with the public key of a user and the public key of at least one recovery agent. The encrypted key information is stored with the file, whereby the user or a recovery agent can decrypt the file data using the private key thereof. When a proper private key is used, encrypted reads from the disk are decrypted transparently by the file system and returned to the user.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: June 19, 2001
    Assignee: Microsoft Corporation
    Inventors: Peter Brundrett, Praerit Garg, Jianrong Gu, James W. Kelly, Jr., Keith S. Kaplan, Robert P. Reichel, Brian Andrew, Gary D. Kimura, Thomas J. Miller
  • Publication number: 20010003057
    Abstract: A II-VI semiconductor device includes a stack of semiconductor layers. An ohmic contact is provided that electrically couples to the stack. The ohmic contact has an oxidation rate when exposed to an oxidizing substance. A passivation capping layer overlies the ohmic contact and has an oxidation rate that is less than the oxidation rate of the ohmic contact.
    Type: Application
    Filed: June 8, 1998
    Publication date: June 7, 2001
    Inventors: FEN-REN CHIEN, MICHAEL A. HAASE, THOMAS J. MILLER
  • Patent number: 6189016
    Abstract: A change journal for recording changes to files in a storage volume of a computer system keeps a record for each notable change to a file. Each record is given a unique update sequence number, which is a serial number of ever-increasing value assigned to each record. Each record includes one or more change reasons specifying what type of action occurred with respect to the associated file. The presence of a close file change reason in a record connotes that the record includes all the notable changes made to the file in a preceding file session, which is defined as the time occurring after the last time a close file change reason was entered in a change record, up to the time of the next succeeding close file change reason. For each file, an entry is made in the storage volume's master file table referencing the change record that currently includes the most up-to-date information on the status of the change reasons for the file.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: February 13, 2001
    Assignee: Microsoft Corporation
    Inventors: Luis Felipe Cabrera, Thomas J. Miller, Brian D. Andrew, Mark J. Zbikowski, Gary D. Kimura
  • Patent number: 6155676
    Abstract: A printhead with improved durability characteristics and a method for making the same. A substrate is provided which includes an ink ejector system and a barrier layer. An orifice plate having a bottom surface made of rhodium is affixed to the barrier layer so that the rhodium-containing bottom surface is securely attached to the barrier layer. The use of rhodium in the bottom surface provides substantially improved adhesion characteristics without the use of separate adhesives or, alternatively, various adhesives may be optionally be employed including polyacrylic acid and silane compositions. The rhodium-containing bottom surface also provides improved corrosion resistance. As a result, a unique printhead is produced having improved structural integrity levels. The orifice plate may likewise have a top surface made of rhodium. The use of a rhodium-containing top surface provides enhanced abrasion resistance and avoids corrosion problems.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: December 5, 2000
    Assignee: Hewlett-Packard Company
    Inventors: H. Thomas Etheridge, III, Thomas J. Miller
  • Patent number: 6151568
    Abstract: A method and apparatus is described which enables a user to analyze an electrical design utilizing a computer. The elements of the electrical design are described at a register transfer level. Embodiments of the invention are described which allow the user to enter the elements described at the register transfer level and estimate the power consumption of portions or all of the electrical design.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: November 21, 2000
    Assignee: Sente, Inc.
    Inventors: David L. Allen, Lorne J. Cooper, Gerald L. Frenkil, Thomas J. Miller
  • Patent number: 6090637
    Abstract: A II-VI semiconductor device includes a stack of II-VI semiconductor layers electrically connected to a top electrical contact. A GaAs substrate is provided which supports the stack of II-VI semiconductor layers and is positioned opposite to the top electrical contacts. A BeTe buffer layer is provided between the GaAs substrate and the stack of II-VI semiconductor layers. The BeTe buffer layer reduces stacking fault defects at the interface between the GaAs substrate and the stack of II-VI semiconductor layers.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: July 18, 2000
    Assignee: 3M Innovative Properties Company
    Inventor: Thomas J. Miller
  • Patent number: 6058123
    Abstract: A II-VI semiconductor device is fabricated using a selective etchant in the form of aqueous solution of HX where X is Cl or Br. The II-VI semiconductor device is composed of a number of layers. Selective etching can be enabled by introducing Mg into one of the semiconductor layers. The resultant device may include a semiconductor layer containing Mg.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: May 2, 2000
    Assignee: 3M Innovative Properties Company
    Inventors: Michael A. Haase, Paul F. Baude, Thomas J. Miller
  • Patent number: 5978815
    Abstract: In order to decrease the overall cost of storing large amounts of data, systems have been developed that use a hierarchy of storage devices from fast local disks to archival off-line storage. Such storage devices may be managed in a hierarchy where data that is accessed only infrequently can be moved to archival storage. The present invention relies on a tight integration of a hierarchical storage manager into the I/O system so that remotely stored attributes can be identified and tracked internally to the I/O system just like any other attributes. Implementations of the present invention may rely on a layered driver model where lower level drivers detect the existence of files with remotely stored attributes and then transfer control for processing I/O requests involving files with remotely stored attributes to higher level drivers. The higher level drivers then assume control to finish processing the I/O request.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: November 2, 1999
    Assignee: Microsoft Corporation
    Inventors: Luis Felipe Cabrera, Gary D. Kimura, Thomas J. Miller, Brian D. Andrew
  • Patent number: 5978814
    Abstract: The present invention provides reliable systems and methods for rapidly determining whether file data streams are the same, or different, without having to make a comparison between the actual data streams. If the determination is made that the data streams are different, the present invention can rapidly determine where the changes between the data streams occur, again, without having to actually compare the entire size of the data streams. Such methods and systems are accomplished by generating a native data signature (NDS) for each data stream stored by the file system, wherein each NDS is substantially smaller in size as compared to the data stream corresponding thereto. The NDS is generated by separating the data stream into a plurality of allocation units, ranging in size from 4K bytes to 256K bytes; by generating a unique change identifier (UCI), one per each allocation unit; and by assembling the UCIs into a series of bits, typically ranging up to, and including, 64 in number.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: November 2, 1999
    Assignee: Microsoft Corporation
    Inventors: Thomas J. Miller, Luis Felipe Cabrera
  • Patent number: 5920895
    Abstract: The efficiency of writing files that are cached using mapped file I/O is improved by suppressing zeroing of uninitialized data in cached pages of a file until the file is mapped by a user mode thread. In an operating system where paging operations are controlled by a virtual memory manager and memory based caching using mapped file I/O is administered by a cache manager, suppressing zeroing of mapped files on writes is implemented by a set of internal operating system interfaces for communications between the virtual memory manager and the cache manager. When a file being cached is not yet mapped by a user mode thread, the cache manager tracks the extent to which a cache page of the file is written so that any uninitialized data in the cache page can later be zeroed when the file is mapped by a user mode thread.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: July 6, 1999
    Assignee: Microsoft Corporation
    Inventors: Frank Louis Perazzoli, Jr., Thomas J. Miller
  • Patent number: 5879962
    Abstract: A method for repeatably fabricating GaAs/ZnSe and other III-V/II-VI semiconductor interfaces with relatively low stacking fault densities in II-VI semiconductor devices such as laser diodes. The method includes providing a molecular beam epitaxy (MBE) system including at least a group III element source, a group II element source, a group V element source and a group VI element source. A semiconductor substrate having a III-V semiconductor surface on which the interface is to be fabricated is positioned within the MBE system. The substrate is then heated to a temperature suitable for III-V semiconductor growth, and a crystalline III-V semiconductor buffer layer grown on the III-V surface of the substrate. The temperature of the semiconductor substrate is then adjusted to a temperature suitable for II-VI semiconductor growth, and a crystalline II-VI semiconductor buffer layer grown on the III-V buffer layer by alternating beam epitaxy.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: March 9, 1999
    Assignee: Minnesota Mining and Manufacturing Company
    Inventors: James M. DePuydt, Michael A. Haase, Kwok-Keung Law, Thomas J. Miller, James M. Gaines, Supratik Guha, Bor-Jen Wu
  • Patent number: D432084
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: October 17, 2000
    Assignee: TMC Enterprise, a division of Tasco Industries, Inc.
    Inventor: Thomas J. Miller
  • Patent number: D434000
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: November 21, 2000
    Assignee: TMC Enterprises, a division of Tasco Industries, Inc.
    Inventor: Thomas J. Miller