Abstract: An arrangement for connecting an array of individual electronic elements into a readily expandable matrix. The arrangement comprises a plurality of matrix slices with each slice including a set number of electronic elements as well as a row and a column buffer. The electronic elements of each matrix slice are diagonally connected to the elements of the adjacent matrix slice.

Abstract: In a telecommunications switching system, a thick film digital span conversion circuit is connected between a digital span and a switching network of the switching system. The circuit converts data, which is encoded for digital span use, to TTL logic coding for use by the switching network. The telecommunications switching system also provides for duplicated data transmission through the switching network. Duplicated conversion circuits are employed in an active/standby configuration under CPU control. The present circuit is relatively small in size and has minimal power consumption.

Abstract: A formatted data message for conveying control information from the peripheral processor of one telecommunications switching system to the peripheral processor of at least one other telecommunications switching system is provided. The data message format comprises a first control work including a plurality of control bits, a data bit and a parity bit for the first control word and a plurality of data words, each data word including a parity bit. The data words contain control information to be conveyed to the receiving peripheral processor. A parity word is included which provides parity for an associated plurality of the preceding data and control words.

Abstract: A transmit data formatter is provided for assembling a plurality of 8-bit data bytes into a data message containing a plurality of message bytes. The transmit data formatter includes a receive buffer which receives a data byte from a peripheral processor. A parallel to serial converter receives the data byte from the receive buffer and outputs the data byte serially. A serial to parallel converter receives the serial data byte and assembles the data byte into a partial message byte when seven data bits have been received. A horizontal parity generator connected to the parallel to serial converter develops a horizontal parity bit which is appended to the seven data bits forming a message byte.

Abstract: A receive data reformatter for a telecommunications switching system is shown for disassembling a data message to a plurality of 8-bit data bytes. The receive data reformatter is comprised of a parallel to serial converter which receives the data message one byte at a time which it subsequently outputs serially. A horizontal parity check circuit receives the serial data and is arranged to output an error signal when an error in parity is detected. A serial to parallel converter, connected to the serial output of the parallel to serial converter, receives the serial data and assembles the serial data into parallel form. A write buffer connected to the serial to parallel converter receives the assembled parallel data when eight data bits have been accumulated in the serial to parallel converter. The thus formed data byte is output to a peripheral processor of the telecommunications switching system.

Abstract: The present invention provides for synchronizing signals transmitted to two duplex copies of hardware from a common source. Signals sent from the source to the duplex copies of hardware may arrive asynchronously at the two copies and require synchronization. In addition, the duplex hardware may be validly operated in the simplex mode of operation, which requires no synchronization of the two hardware copies.

Abstract: In a PCM telecommunications switching system, an arrangement for deriving a clock signal from incoming PCM data of a digital span is shown. This derived clock signal is synchronized and continuously locked to the incoming PCM data of the digital span. The present digital phase locking arrangement cyclically adjusts the derive clock signal so that on the average synchronism is maintained.

Abstract: This circuit provides for synchronizing the internal clocks of at least two central processing unit process controllers. In order to synchronize the internal clocks of these central processing units (CPUs), the CPUs periodically execute a predetermined set of operating instructions which cause their internal clocks to coincide. This synchronization function is dynamic in that it is continually performed in an on-line fashion while the processors are performing their telecommunication process control function.

Abstract: An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link processor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.

Abstract: In a telecommunications switching system, a thick film digital span conversion circuit is connected between a digital span and a switching network of the switching system. The circuit converts data, which is encoded for digital span use, to TTL logic coding for use by the switching network. The telecommunications switching system provides for duplicated data transmission through the switching network. Duplicated conversion circuits are employed in an active/standby configuration under CPU control. On-line replacement of a fault conversion circuit may be performed without a switching service interruption.

Abstract: In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span reframing circuit continuously reframes and resynchronizes each of the digital spans that are detected as lacking proper framing. The digital span reframing circuit realigns both framing and super framing, TS bits and FS bits, for proper digital span reception.

Abstract: A remote data link controller is disclosed for formatting, transmitting and receiving control data over high speed digital data links between the peripheral processors of a plurality of telecommunications switching systems. The remote data link controller includes a microprocessor controlled data link processing circuit which is time shared among all of the digital data links. The remote data link controller processes one transmit and one receive message byte during a reformatting cycle for each digital data link. It stores any intermediate results in a temporary memory than proceeds to service the next digital data link. The remote data link controller fetches intermediate results from the temporary memory, processes the data and stores the next intermediate results in the temporary memory until it has completely serviced all of the digital data links.

Abstract: In a telecommunications switching system, a thick film digital span transmission circuit is connected between a digital span and a switching network of the switching system. The circuit converts unipolar switching network data to bipolar data for digital span use. The present circuit is relatively small in size and has minimal power consumption. This circuit also provides for attenuating and shaping the pulses transmitted to the digital span.

Abstract: In a telecommunications switching system, a thick film digital span circuit arrangement is connected between a digital span and a switching network of the switching system. The transmission circuit arrangement converts unipolar switching network data to bipolar data for use by the digital span. The telecommunications switching system provides for duplicated data transmission to the digital span. Duplicated transmission circuits are arranged in an active/standby configuration under CPU control without affecting the overall impedance seen by the digital span.

Abstract: In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span frame detection circuit continuously monitors the framing of each of the digital spans. The digital span frame detection circuit checks for both proper framing and super framing, TS bits and FS bits. An ordered examination of each of the number of digital spans will occur. Any digital span which lacks proper framing or super framing will be marked for subsequent processing. These markings will be scanned and submitted for reframing in an ordered fashion.

Abstract: In a PCM switching system having a CPU controlled switching network, a reformatting circuit is connected between the switching network and a number of digital spans. The reformatting circuit converts supervisory data which is serially received to parallel data words which may be readily accessed by the CPU. The supervisory data is logically ordered and stored in a memory for CPU access.

Abstract: An allocation controller providing for equal priority sharing of multiple resources by a plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to one of the common resources are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: An allocation controller providing for equal priority sharing of duplicate copy multiple resources by a duplex plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to one of the common resources are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: An arbitration controller providing for equal priority sharing of a resource by a plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: An arbitration controller providing for equal priority sharing of a resource by a plurality of central processing units. Conflicts resulting from simultaneous requests from several CPU's for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.