Patents by Inventor Thomas Jew
Thomas Jew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7483327Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.Type: GrantFiled: March 2, 2006Date of Patent: January 27, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, James D. Burnett, Jack M. Higman, Thomas Jew
-
Publication number: 20090016140Abstract: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Inventors: Qadeer A. Qureshi, Sushama Davar, Thomas Jew
-
Publication number: 20080247255Abstract: An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.Type: ApplicationFiled: April 3, 2007Publication date: October 9, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ronald J. Syzdek, Gowrishankar L. Chindalore, Thomas Jew
-
Patent number: 7428172Abstract: A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.Type: GrantFiled: July 17, 2006Date of Patent: September 23, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Jon S. Choy, David W. Chrudimsky, Thomas Jew
-
Publication number: 20080013384Abstract: A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.Type: ApplicationFiled: July 17, 2006Publication date: January 17, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Jon S. Choy, David W. Chrudimsky, Thomas Jew
-
Publication number: 20070285986Abstract: Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of 0's or 1's for a specified voltage. As the range of addresses are scanned across a range of voltages, the instances of the count value being counted is accumulated by the bit counter. Automated Tester Equipment (ATE) reads the accumulated count value for each tested voltage.Type: ApplicationFiled: June 7, 2006Publication date: December 13, 2007Inventors: Richard K. Eguchi, Larry J. Grieve, Thomas Jew
-
Publication number: 20070220388Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.Type: ApplicationFiled: March 2, 2006Publication date: September 20, 2007Inventors: Qadeer Quereshi, James Burnett, Jack Higman, Thomas Jew
-
Patent number: 7269090Abstract: A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.Type: GrantFiled: January 30, 2001Date of Patent: September 11, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Frank K. Baker, Jr., James D. Burnett, Thomas Jew
-
Patent number: 7245527Abstract: A non-volatile memory system (230) includes a magnetoresistive random access memory (MRAM) (232) including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory (234) including a plurality of floating-gate memory cells, and a controller (236) coupled to the MRAM (232) and to the floating-gate nonvolatile memory (234). The controller (236) is adapted to be coupled to a system bus (220) and controls a selected one of the MRAM (232) and the floating-gate nonvolatile memory (234) in response to an access initiated from the system bus (220).Type: GrantFiled: May 16, 2005Date of Patent: July 17, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, Thomas Jew, Curtis F. Wyman
-
Publication number: 20060256610Abstract: A non-volatile memory system (230) includes a magnetoresistive random access memory (MRAM) (232) including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory (234) including a plurality of floating-gate memory cells, and a controller (236) coupled to the MRAM (232) and to the floating-gate nonvolatile memory (234). The controller (236) is adapted to be coupled to a system bus (220) and controls a selected one of the MRAM (232) and the floating-gate nonvolatile memory (234) in response to an access initiated from the system bus (220).Type: ApplicationFiled: May 16, 2005Publication date: November 16, 2006Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Qadeer Qureshi, Thomas Jew, Curtis Wyman
-
Publication number: 20020103959Abstract: A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.Type: ApplicationFiled: January 30, 2001Publication date: August 1, 2002Inventors: Frank K. Baker, James D. Burnett, Thomas Jew
-
Patent number: 6226200Abstract: An apparatus and method for operating a non-volatile memory including an array of bit cells. A selection is made between an operational power supply and a test power supply, the test power supply being on-chip programmable. The non-volatile memory is operated in a operational mode if the operational power supply is selected, and in a test mode if the test power supply is selected.Type: GrantFiled: November 17, 1999Date of Patent: May 1, 2001Assignee: Motorola Inc.Inventors: Richard Kazuki Eguchi, David William Chrudimsky, Thomas Jew
-
Patent number: 6101130Abstract: An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).Type: GrantFiled: June 29, 1999Date of Patent: August 8, 2000Assignee: Motorola Inc.Inventors: Frank Kelsey Baker, Juan Buxo, Danny Pak-Chum Shum, Thomas Jew
-
Patent number: 6008677Abstract: A method an apparatus for performing a reset operation in an integrated circuit where a memory programming voltage is recovered allowing use of the memory during reset. The voltage recovery unit includes a high voltage conversion portion active for a first recovery period, and a low voltage conversion portion active for a subsequent second recovery period, the low voltage conversion portion is inactive for the first recovery period. The first and second recovery portions are responsive to assertion of a reset signal and an intermediate reset signal generated before the end of the reset period. Recovery of the programming voltage allows uncorrupted retrieval and use of a configuration word during reset. The high voltage conversion portion includes p-channel devices with robust breakdown resistance, and the low voltage conversion portion includes n-channel devices which provides improved speed of operation.Type: GrantFiled: April 2, 1998Date of Patent: December 28, 1999Assignee: Motorola, Inc.Inventors: Cheri Lynn Harrington, Thomas Jew, Kishna Weaver, Thomas R. Toms, Yongliang Wang
-
Patent number: 5991201Abstract: A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.Type: GrantFiled: April 27, 1998Date of Patent: November 23, 1999Assignee: Motorola Inc.Inventors: Clinton C. K. Kuo, Thomas Jew, David W. Chrudimsky
-
Patent number: 5737566Abstract: A data processing system having a memory with a low power operating mode and a method of operation is described. An static random access memory (SRAM) (18) having a low power operating mode is provided for a data processing system (10). A programmable control bit is used for switching the SRAM (18) from a one clock cycle operating mode to a two clock cycle, or low power, operating mode. Initially, during the two cycle operating mode, only a bus interface unit (41) is active. During the first cycle, an address is compared to determine if the address is a valid address. If the address is valid, address decoders (42) are enabled, and a data transfer is completed on the second clock cycle. If the address is not valid, the address decoders (42) remain disabled and memory array (43) remains in a quiescent state consuming minimum power. During one cycle mode, the SRAM (18) decodes every address in order to respond in one clock cycle to a valid address.Type: GrantFiled: December 20, 1993Date of Patent: April 7, 1998Assignee: Motorola, Inc.Inventors: Robert Wayne Sparks, Wallace Baker Harwood, III, Thomas Jew, James Bradley Eifert