Patents by Inventor Thomas Kilger
Thomas Kilger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11823970Abstract: A radar chip package includes a radar monolithic microwave integrated circuit (MMIC) having a backside, a frontside arranged opposite to the backside, and lateral sides that extend between the backside and the frontside, wherein the radar MIMIC comprises a recess that extends from the backside at least partially towards the frontside; a plurality of electrical interfaces coupled to the frontside of the radar MIMIC; at least one antenna arranged at the frontside of the radar MIMIC; and a lens formed over the recess and the at least one antenna, wherein the lens is coupled to the backside of the radar MMIC.Type: GrantFiled: May 5, 2021Date of Patent: November 21, 2023Assignee: Infineon Technologies AGInventors: Bernhard Rieder, Thomas Kilger
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Publication number: 20220359328Abstract: A radar chip package includes a radar monolithic microwave integrated circuit (MMIC) having a backside, a frontside arranged opposite to the backside, and lateral sides that extend between the backside and the frontside, wherein the radar MIMIC comprises a recess that extends from the backside at least partially towards the frontside; a plurality of electrical interfaces coupled to the frontside of the radar MIMIC; at least one antenna arranged at the frontside of the radar MIMIC; and a lens formed over the recess and the at least one antenna, wherein the lens is coupled to the backside of the radar MMIC.Type: ApplicationFiled: May 5, 2021Publication date: November 10, 2022Applicant: Infineon Technologies AGInventors: Bernhard RIEDER, Thomas KILGER
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Radio-frequency device with radio-frequency signal carrying element and associated production method
Patent number: 11416730Abstract: A radio-frequency device comprises a radio-frequency chip, a first connecting element arranged over a chip surface of the radio-frequency chip, the first connecting element being designed to mechanically and electrically connect the radio-frequency chip to a circuit board, and a radio-frequency signal carrying element arranged over the chip surface and electrically coupled to the radio-frequency chip, the radio-frequency signal carrying element being covered by an electrically nonconductive material and being designed to transmit a signal in a direction parallel to the chip surface, wherein the first connecting element and the radio-frequency signal carrying element are arranged at a same level in relation to a direction perpendicular to the chip surface, and wherein the first connecting element is spaced apart from the radio-frequency signal carrying element by way of a region that is free of the electrically nonconductive material.Type: GrantFiled: October 15, 2020Date of Patent: August 16, 2022Assignee: Infineon Technologies AGInventors: Bernhard Rieder, Thomas Kilger -
Publication number: 20220148951Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.Type: ApplicationFiled: December 7, 2021Publication date: May 12, 2022Applicant: Infineon Technologies AGInventors: Ngoc-Hoa Huynh, Franz-Xaver Muehlbauer, Claus Waechter, Veronika Theyerl, Dominic Maier, Thomas Kilger, Saverio Trotta, Ashutosh Baheti, Georg Meyer-Berg, Maciej Wojnowski
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Patent number: 11195787Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.Type: GrantFiled: February 17, 2016Date of Patent: December 7, 2021Assignee: Infineon Technologies AGInventors: Ngoc-Hoa Huynh, Franz-Xaver Muehlbauer, Claus Waechter, Veronika Huber, Dominic Maier, Thomas Kilger, Saverio Trotta, Ashutosh Baheti, Georg Meyer-Berg, Maciej Wojnowski
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RADIO-FREQUENCY DEVICE WITH RADIO-FREQUENCY SIGNAL CARRYING ELEMENT AND ASSOCIATED PRODUCTION METHOD
Publication number: 20210125021Abstract: A radio-frequency device comprises a radio-frequency chip, a first connecting element arranged over a chip surface of the radio-frequency chip, the first connecting element being designed to mechanically and electrically connect the radio-frequency chip to a circuit board, and a radio-frequency signal carrying element arranged over the chip surface and electrically coupled to the radio-frequency chip, the radio-frequency signal carrying element being covered by an electrically nonconductive material and being designed to transmit a signal in a direction parallel to the chip surface, wherein the first connecting element and the radio-frequency signal carrying element are arranged at a same level in relation to a direction perpendicular to the chip surface, and wherein the first connecting element is spaced apart from the radio-frequency signal carrying element by way of a region that is free of the electrically nonconductive material.Type: ApplicationFiled: October 15, 2020Publication date: April 29, 2021Inventors: Bernhard RIEDER, Thomas KILGER -
Patent number: 10930541Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.Type: GrantFiled: January 16, 2019Date of Patent: February 23, 2021Assignee: Infineon Technologies AGInventors: Thomas Kilger, Francesca Arcioni, Maciej Wojnowski
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Patent number: 10626012Abstract: A semiconductor device having a lid, and method of making a semiconductor device having a lid is disclosed. The semiconductor device includes a substrate. A device is positioned at the substrate. A lid made of a semiconductor material is positioned over the device to form a protective cavity about the device. The lid is formed using a semiconductor process. In other examples, the lid may be made of a nonconductive material, such as a polymer material. The lids may be formed as part of a batch process.Type: GrantFiled: April 13, 2015Date of Patent: April 21, 2020Assignee: Infineon Technologies AGInventors: Franz-Xaver Muehlbauer, Dominic Maier, Thomas Kilger
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Patent number: 10549985Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.Type: GrantFiled: August 31, 2017Date of Patent: February 4, 2020Assignee: Infineon Technologies AGInventors: Dominic Maier, Matthias Steiert, Chau Fatt Chiang, Christian Geissler, Bernd Goller, Thomas Kilger, Johannes Lodermeyer, Franz-Xaver Muehlbauer, Chee Yang Ng, Beng Keh See, Claus Waechter
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Publication number: 20190221465Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.Type: ApplicationFiled: January 16, 2019Publication date: July 18, 2019Inventors: Thomas Kilger, Francesca Arcioni, Maciej Wojnowski
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Publication number: 20190198455Abstract: A semiconductor apparatus comprises: a circuit board; a semiconductor package having a main surface, wherein the semiconductor package is arranged on the circuit board and the main surface faces the circuit board; a radio-frequency line element of the semiconductor package, which radio-frequency line element is arranged on the main surface or inside the semiconductor package, wherein the radio-frequency line element is designed to transmit a signal at a frequency of greater than 10 GHz; and an underfiller material arranged between the circuit board and the semiconductor package, wherein the radio-frequency line element and the underfiller material do not overlap in an orthogonal projection onto the main surface.Type: ApplicationFiled: December 20, 2018Publication date: June 27, 2019Inventors: Walter HARTNER, Christian GEISSLER, Thomas KILGER, Johannes LODERMEYER, Franz-Xaver MUEHLBAUER, Martin Richard NIESSNER, Claus WAECHTER
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Patent number: 10224317Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.Type: GrantFiled: June 9, 2017Date of Patent: March 5, 2019Assignee: INFINEON TECHNOLOGIES AGInventor: Thomas Kilger
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Publication number: 20180148322Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.Type: ApplicationFiled: August 31, 2017Publication date: May 31, 2018Inventors: Dominic Maier, Matthias Steiert, Chau Fatt Chiang, Christian Geissler, Bernd Goller, Thomas Kilger, Johannes Lodermeyer, Franz-Xaver Muehlbauer, Chee Yang Ng, Beng Keh See, Claus Waechter
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Patent number: 9981843Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.Type: GrantFiled: April 26, 2016Date of Patent: May 29, 2018Assignee: Infineon Technologies AGInventors: Dominic Maier, Alfons Dehe, Thomas Kilger, Markus Menath, Franz Xaver Muehlbauer, Daniel Porwol, Juergen Wagner
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Patent number: 9806056Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.Type: GrantFiled: February 15, 2016Date of Patent: October 31, 2017Assignee: Infineon Technologies AGInventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
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Publication number: 20170278836Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.Type: ApplicationFiled: June 9, 2017Publication date: September 28, 2017Inventor: Thomas Kilger
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Publication number: 20170236776Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.Type: ApplicationFiled: February 17, 2016Publication date: August 17, 2017Applicant: Infineon Technologies AGInventors: Ngoc-Hoa Huynh, Franz-Xaver Muehlbauer, Claus Waechter, Veronika Huber, Dominic Maier, Thomas Kilger, Saverio Trotta, Ashutosh Baheti, Georg Meyer-Berg, Maciej Wojnowski
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Patent number: 9725303Abstract: A semiconductor device includes a microelectromechanical system (MEMS) die, an encapsulation material, a via element, a non-conductive lid, and a conductive layer. The encapsulation material laterally surrounds the MEMS die. The via element extends through the encapsulation material. The non-conductive lid is over the MEMS die and defines a cavity. The conductive layer is over the MEMS die and the encapsulation material and is electrically coupled to the via element.Type: GrantFiled: March 16, 2016Date of Patent: August 8, 2017Assignee: Infineon Technologies AGInventors: Dominic Maier, Franz-Xaver Muehlbauer, Thomas Kilger
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Patent number: 9718678Abstract: According to various embodiments, a package arrangement may include: a first encapsulation material; at least one electronic circuit at least partially embedded in the first encapsulation material, the at least one electronic circuit including a first contact pad structure at a first side of the at least one electronic circuit; at least one electromechanical device disposed over the first side of the at least one electronic circuit, the at least one electromechanical device including a second contact pad structure facing the first side of the at least one electronic circuit; a redistribution layer structure between the at least one electromechanical device and the at least one electronic circuit, the redistribution layer structure electrically connecting the first contact pad structure with the second contact pad structure, wherein a gap is provided between the at least one electromechanical device and the redistribution layer structure; a second encapsulation material at least partially covering the at leastType: GrantFiled: September 25, 2014Date of Patent: August 1, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Ulrich Wachter, Thomas Kilger
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Patent number: 9704843Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.Type: GrantFiled: September 14, 2015Date of Patent: July 11, 2017Assignee: Infineon Technologies AGInventor: Thomas Kilger