Patents by Inventor Thomas Kilger

Thomas Kilger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210125021
    Abstract: A radio-frequency device comprises a radio-frequency chip, a first connecting element arranged over a chip surface of the radio-frequency chip, the first connecting element being designed to mechanically and electrically connect the radio-frequency chip to a circuit board, and a radio-frequency signal carrying element arranged over the chip surface and electrically coupled to the radio-frequency chip, the radio-frequency signal carrying element being covered by an electrically nonconductive material and being designed to transmit a signal in a direction parallel to the chip surface, wherein the first connecting element and the radio-frequency signal carrying element are arranged at a same level in relation to a direction perpendicular to the chip surface, and wherein the first connecting element is spaced apart from the radio-frequency signal carrying element by way of a region that is free of the electrically nonconductive material.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 29, 2021
    Inventors: Bernhard RIEDER, Thomas KILGER
  • Patent number: 10930541
    Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Francesca Arcioni, Maciej Wojnowski
  • Patent number: 10626012
    Abstract: A semiconductor device having a lid, and method of making a semiconductor device having a lid is disclosed. The semiconductor device includes a substrate. A device is positioned at the substrate. A lid made of a semiconductor material is positioned over the device to form a protective cavity about the device. The lid is formed using a semiconductor process. In other examples, the lid may be made of a nonconductive material, such as a polymer material. The lids may be formed as part of a batch process.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Franz-Xaver Muehlbauer, Dominic Maier, Thomas Kilger
  • Patent number: 10549985
    Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dominic Maier, Matthias Steiert, Chau Fatt Chiang, Christian Geissler, Bernd Goller, Thomas Kilger, Johannes Lodermeyer, Franz-Xaver Muehlbauer, Chee Yang Ng, Beng Keh See, Claus Waechter
  • Publication number: 20190221465
    Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 18, 2019
    Inventors: Thomas Kilger, Francesca Arcioni, Maciej Wojnowski
  • Publication number: 20190198455
    Abstract: A semiconductor apparatus comprises: a circuit board; a semiconductor package having a main surface, wherein the semiconductor package is arranged on the circuit board and the main surface faces the circuit board; a radio-frequency line element of the semiconductor package, which radio-frequency line element is arranged on the main surface or inside the semiconductor package, wherein the radio-frequency line element is designed to transmit a signal at a frequency of greater than 10 GHz; and an underfiller material arranged between the circuit board and the semiconductor package, wherein the radio-frequency line element and the underfiller material do not overlap in an orthogonal projection onto the main surface.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Inventors: Walter HARTNER, Christian GEISSLER, Thomas KILGER, Johannes LODERMEYER, Franz-Xaver MUEHLBAUER, Martin Richard NIESSNER, Claus WAECHTER
  • Patent number: 10224317
    Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: March 5, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Thomas Kilger
  • Publication number: 20180148322
    Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.
    Type: Application
    Filed: August 31, 2017
    Publication date: May 31, 2018
    Inventors: Dominic Maier, Matthias Steiert, Chau Fatt Chiang, Christian Geissler, Bernd Goller, Thomas Kilger, Johannes Lodermeyer, Franz-Xaver Muehlbauer, Chee Yang Ng, Beng Keh See, Claus Waechter
  • Patent number: 9981843
    Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventors: Dominic Maier, Alfons Dehe, Thomas Kilger, Markus Menath, Franz Xaver Muehlbauer, Daniel Porwol, Juergen Wagner
  • Patent number: 9806056
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20170278836
    Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventor: Thomas Kilger
  • Publication number: 20170236776
    Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Applicant: Infineon Technologies AG
    Inventors: Ngoc-Hoa Huynh, Franz-Xaver Muehlbauer, Claus Waechter, Veronika Huber, Dominic Maier, Thomas Kilger, Saverio Trotta, Ashutosh Baheti, Georg Meyer-Berg, Maciej Wojnowski
  • Patent number: 9725303
    Abstract: A semiconductor device includes a microelectromechanical system (MEMS) die, an encapsulation material, a via element, a non-conductive lid, and a conductive layer. The encapsulation material laterally surrounds the MEMS die. The via element extends through the encapsulation material. The non-conductive lid is over the MEMS die and defines a cavity. The conductive layer is over the MEMS die and the encapsulation material and is electrically coupled to the via element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Dominic Maier, Franz-Xaver Muehlbauer, Thomas Kilger
  • Patent number: 9718678
    Abstract: According to various embodiments, a package arrangement may include: a first encapsulation material; at least one electronic circuit at least partially embedded in the first encapsulation material, the at least one electronic circuit including a first contact pad structure at a first side of the at least one electronic circuit; at least one electromechanical device disposed over the first side of the at least one electronic circuit, the at least one electromechanical device including a second contact pad structure facing the first side of the at least one electronic circuit; a redistribution layer structure between the at least one electromechanical device and the at least one electronic circuit, the redistribution layer structure electrically connecting the first contact pad structure with the second contact pad structure, wherein a gap is provided between the at least one electromechanical device and the redistribution layer structure; a second encapsulation material at least partially covering the at least
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 1, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ulrich Wachter, Thomas Kilger
  • Patent number: 9704843
    Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies AG
    Inventor: Thomas Kilger
  • Patent number: 9487392
    Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20160311679
    Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 27, 2016
    Inventors: Dominic Maier, Alfons Dehe, Thomas Kilger, Markus Menath, Franz Xaver Muehlbauer, Daniel Porwol, Juergen Wagner
  • Publication number: 20160297672
    Abstract: A semiconductor device having a lid, and method of making a semiconductor device having a lid is disclosed. The semiconductor device includes a substrate. A device is positioned at the substrate. A lid made of a semiconductor material is positioned over the device to form a protective cavity about the device. The lid is formed using a semiconductor process. In other examples, the lid may be made of a nonconductive material, such as a polymer material. The lids may be formed as part of a batch process.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 13, 2016
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Franz-Xaver Muehlbauer, Dominic Maier, Thomas Kilger
  • Publication number: 20160163674
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20160090294
    Abstract: According to various embodiments, a package arrangement may include: a first encapsulation material; at least one electronic circuit at least partially embedded in the first encapsulation material, the at least one electronic circuit including a first contact pad structure at a first side of the at least one electronic circuit; at least one electromechanical device disposed over the first side of the at least one electronic circuit, the at least one electromechanical device including a second contact pad structure facing the first side of the at least one electronic circuit; a redistribution layer structure between the at least one electromechanical device and the at least one electronic circuit, the redistribution layer structure electrically connecting the first contact pad structure with the second contact pad structure, wherein a gap is provided between the at least one electromechanical device and the redistribution layer structure; a second encapsulation material at least partially covering the at least
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Ulrich Wachter, Thomas Kilger