Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

Abstract: Techniques are generally described for mapping a thread onto heterogeneous processor cores. Example techniques may include associating the thread with one or more predefined execution characteristics, assigning the thread to one or more heterogeneous processor cores based on the one or more predefined execution characteristics, and/or executing the thread by the respective assigned heterogeneous processor cores.

Abstract: Examples of sensing a human touch to a touch screen and providing tactile and visual feedback are disclosed.

Abstract: Examples of sensing a human touch to a touch screen and providing tactile and visual feedback are disclosed.

Abstract: An operating system sandbox may include an operating system isolation module configured to restrict an operating system from transmitting machine-readable data and/or machine-readable instructions to an application, based on at least one predefined rule corresponding to abnormal operating system behavior.

Abstract: Techniques are generally described for allocating a thread to heterogeneous processor cores. Example techniques may include monitoring real time computing data related to the heterogeneous processor cores processing the thread, allocating the thread to the heterogeneous processor cores based, at least in part, on the real time computing data, and/or executing the thread by the respective allocated heterogeneous processor core.

Abstract: Implementations related to power reduction in physical layer wireless communications are disclosed.

Abstract: Implementations related to robust multipath routing are disclosed.

Abstract: Implementations related to robust multipath routing are disclosed.

Abstract: Implementations related to robust multipath routing are disclosed.

Abstract: Interactive devices for detecting, characterizing, and acting upon tactile inputs are disclosed. An example embodiment may include a doll configured to produce audible outputs, visible outputs, and/or movement based at least in part upon its characterization of a tactile input. For example, the doll may characterize a tactile input as a slap, a tickle, a rub, a pinch, etc., and the doll may cry, smile, giggle, or move based upon its characterization of the tactile input.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: Techniques are generally described for mapping a thread onto heterogeneous processor cores. Example techniques may include associating the thread with one or more predefined execution characteristic(s), assigning the thread to one or more heterogeneous processor core(s) based on the one or more predefined execution characteristic(s), and/or executing the thread by the respective assigned heterogeneous processor core(s).

Abstract: An operating system sandbox may include an operating system isolation module configured to restrict an operating system from transmitting machine-readable data and/or machine-readable instructions to an application, based on at least one predefined rule corresponding to abnormal operating system behavior.

Abstract: Techniques for pre-filling a cache associated with a second core prior to migration of a thread from a first core to the second core are generally disclosed. The present disclosure contemplates that some computer systems may include a plurality of processor cores, and that some cores may have hardware capabilities different from other cores. In order to assign threads to appropriate cores, thread/core mapping may be utilized and, in some cases, a thread may be reassigned from one core to another core. In a probabilistic anticipation that a thread may be migrated from a first core to a second core, a cache associated with the second core may be pre-filled (e.g., may become filled with some data before the thread is rescheduled on the second core). Such a cache may be a local cache to the second core and/or an associated buffer cache, for example.

Abstract: Techniques are generally described for allocating a thread to heterogeneous processor cores. Example techniques may include monitoring real time computing data related to the heterogeneous processor cores processing the thread, allocating the thread to the heterogeneous processor cores based, at least in part, on the real time computing data, and/or executing the thread by the respective allocated heterogeneous processor core.

Abstract: Interactive devices for detecting, characterizing, and acting upon tactile inputs are disclosed. An example embodiment may include a doll configured to produce audible outputs, visible outputs, and/or movement based at least in part upon its characterization of a tactile input. For example, the doll may characterize a tactile input as a slap, a tickle, a rub, a pinch, etc., and the doll may cry, smile, giggle, or move based upon its characterization of the tactile input.

Abstract: Times at which certain tasks are performed by a computer system, such as a data storage center, may be selected to reduce the cost of electrical energy in running the tasks. Tasks may be performed when the cost of electrical energy is relatively low. Alternatively, or in addition, tasks may be performed when there is a reduced call for air conditioning to cool the electronics of the computer system.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.