Patents by Inventor Thomas M. Conte

Thomas M. Conte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Robust Multipath Routing
    Publication number: 20100309841
    Abstract: Implementations related to robust multipath routing are disclosed.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 9, 2010
    Inventor: Thomas M. Conte
  • Touch Screen with Tactile Feedback
    Publication number: 20100308983
    Abstract: Examples of sensing a human touch to a touch screen and providing tactile and visual feedback are disclosed.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 9, 2010
    Inventors: Thomas M. Conte, Bill Mangione-Smith
  • Power Reduction in Physical Layer Wireless Communications
    Publication number: 20100215129
    Abstract: Implementations related to power reduction in physical layer wireless communications are disclosed.
    Type: Application
    Filed: February 23, 2009
    Publication date: August 26, 2010
    Inventor: Thomas M. Conte
  • Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture
    Patent number: 7028286
    Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: April 11, 2006
    Assignee: PTS Corporation
    Inventors: Sergei Yurievich Larin, Gerald George Pechanek, Thomas M. Conte
  • Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture
    Publication number: 20040015931
    Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.
    Type: Application
    Filed: April 10, 2002
    Publication date: January 22, 2004
    Applicant: BOPS, Inc.
    Inventors: Sergei Yurievich Larin, Gerald George Pechanek, Thomas M. Conte