Patents by Inventor Thomas M. Graettinger
Thomas M. Graettinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8470716Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: GrantFiled: November 3, 2011Date of Patent: June 25, 2013Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Thomas M. Graettinger
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Patent number: 8228743Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: February 10, 2011Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A Weimer, Arup Bhattacharyya
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Publication number: 20120168903Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.Type: ApplicationFiled: March 6, 2012Publication date: July 5, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: H. Montgomery Manning, Thomas M. Graettinger
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Patent number: 8154064Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.Type: GrantFiled: August 10, 2010Date of Patent: April 10, 2012Assignee: Micron Technology, Inc.Inventors: H. Montgomery Manning, Thomas M. Graettinger
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Publication number: 20120052650Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: ApplicationFiled: November 3, 2011Publication date: March 1, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Kevin R. Shea, Thomas M. Graettinger
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Patent number: 8076248Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: GrantFiled: January 6, 2010Date of Patent: December 13, 2011Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Thomas M. Graettinger
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Patent number: 7989289Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.Type: GrantFiled: June 30, 2008Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Tejas Krishnamohan, Krishna Parat, Kyu Min, Srivardhan Gowda, Thomas M. Graettinger, Nirmal Ramaswamy
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Publication number: 20110147827Abstract: The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: Fatma Arzum Simsek-Ege, Sanh Tang, Nirmal Ramaswamy, Thomas M. Graettinger, Kyu S. Min, Tejas Krishnamohan, Srivardhan Gowda
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Publication number: 20110133268Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: ApplicationFiled: February 10, 2011Publication date: June 9, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D.V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Patent number: 7898850Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: October 12, 2007Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Publication number: 20100320566Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.Type: ApplicationFiled: August 10, 2010Publication date: December 23, 2010Inventors: H. Montgomery Manning, Thomas M. Graettinger
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Patent number: 7781818Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.Type: GrantFiled: November 9, 2006Date of Patent: August 24, 2010Assignee: Micron Technology, Inc.Inventors: H. Montgomery Manning, Thomas M. Graettinger
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Patent number: 7736987Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.Type: GrantFiled: May 1, 2007Date of Patent: June 15, 2010Assignee: Micron Technology, Inc.Inventors: H. Montgomery Manning, Thomas M. Graettinger
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Publication number: 20100105186Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: ApplicationFiled: January 6, 2010Publication date: April 29, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Kevin R. Shea, Thomas M. Graettinger
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Patent number: 7687844Abstract: The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.Type: GrantFiled: March 20, 2008Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventors: Cancheepuram V. Srividya, F. Daniel Gealy, Thomas M. Graettinger
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Patent number: 7683413Abstract: A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.Type: GrantFiled: September 7, 2006Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventors: Thomas M. Graettinger, Marsela Pontoh, Thomas A. Figura
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Patent number: 7666797Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: GrantFiled: August 17, 2006Date of Patent: February 23, 2010Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Thomas M. Graettinger
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Publication number: 20090321809Abstract: Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: Nirmal Ramaswamy, Tejas Krishnamohan, Kyu Min, Thomas M. Graettinger
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Publication number: 20090283817Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.Type: ApplicationFiled: June 30, 2008Publication date: November 19, 2009Inventors: Tejas Krishnamohan, Krishna Parat, Kyu Min, Srivardhan Gowda, Thomas M. Graettinger, Nirmal Ramaswamy
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Patent number: 7535695Abstract: The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and nitrogen. The layer containing titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: August 15, 2006Date of Patent: May 19, 2009Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Thomas M. Graettinger