Patents by Inventor Thomas M. Graettinger

Thomas M. Graettinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7125781
    Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: October 24, 2006
    Assignee: Micron Technology, Inc.
    Inventors: H. Montgomery Manning, Thomas M. Graettinger, Marsela Pontoh
  • Patent number: 7126182
    Abstract: The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is commonly shared among at least some of the plurality of memory cell capacitors within the memory array. The cell electrode within the memory array includes a conductor metal layer including at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride. Polysilicon is received over the conductor metal layer. The conductor metal layer and the polysilicon are received over the storage node electrodes of said at least some of the plurality of memory cell capacitors. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: October 24, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Thomas M. Graettinger
  • Patent number: 7105403
    Abstract: A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Thomas M. Graettinger, Marsela Pontoh, Thomas A. Figura
  • Patent number: 7092234
    Abstract: The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and nitrogen. The layer containing titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: August 15, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Thomas M. Graettinger
  • Patent number: 7091101
    Abstract: A method of forming a device is disclosed. The method includes forming a capacitor, and forming the capacitor includes forming a first electrode. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. Forming the capacitor also includes forming a dielectric on the first electrode, and forming a second electrode on the dielectric. The second electrode includes at least one non-smooth surface.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: August 15, 2006
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 7041570
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a first substrate layer, and forming a first electrode on the first substrate layer. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method also includes forming a dielectric on the first electrode and the first substrate layer, and forming a second electrode on the dielectric and the first substrate layer. The second electrode includes at least one non-smooth surface. The method further includes forming a second substrate layer on the second electrode.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 9, 2006
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 7033884
    Abstract: The invention includes capacitor constructions comprising a layer of aluminum oxide between a high-k dielectric material and a layer comprising titanium and nitrogen. The layer comprising titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: April 25, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Thomas M. Graettinger
  • Patent number: 7026222
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a substrate assembly, and forming a first electrode on the substrate assembly. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method further includes forming a dielectric on the first electrode and an uppermost surface of the substrate assembly, and forming a second electrode on the dielectric and the uppermost surface of the substrate assembly. The second electrode includes at least one non-smooth surface.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 7023043
    Abstract: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Howard E. Rhodes, Gurtej Sandhu, F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 6964901
    Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: November 15, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Marsela Pontoh, Cem Basceri, Thomas M. Graettinger
  • Patent number: 6960513
    Abstract: A capacitor including a first electrode selected from a group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof. The capacitor also includes a second electrode and a dielectric between the first and second electrodes. The present invention may be used to form devices, such as memory devices and processors. The present invention also includes a method of making a capacitor. The method includes forming a first electrode selected from a group consisting of transition metals, conductive metal-oxides, and alloys thereof. The method also includes forming a second electrode and forming a dielectric between the first and second electrodes.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: November 1, 2005
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 6919257
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a first electrode having a non-smooth surface and selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method further includes forming a second electrode, and forming a dielectric between the first and second electrodes.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: July 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 6881642
    Abstract: A method of forming an MIM capacitor with low leakage and high capacitance is disclosed. A layer of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) material is formed as a lower electrode over an optional capacitance layer of hemispherical grained polysilicon (HSG). Prior to the dielectric formation, the first layer may be optionally subjected to a nitridization or oxidation process. A dielectric layer of, for example, aluminum oxide (Al2O3) formed by atomic layer deposition (ALD) is fabricated over the first layer and after the optional nitridization or oxidation process. An upper electrode of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) is formed over the dielectric layer.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Thomas M. Graettinger
  • Patent number: 6858894
    Abstract: The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: February 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Cancheepuram V. Srividya, F. Daniel Gealy, Thomas M. Graettinger
  • Publication number: 20040245559
    Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.
    Type: Application
    Filed: May 6, 2004
    Publication date: December 9, 2004
    Inventors: Marsela Pontoh, Cem Basceri, Thomas M. Graettinger
  • Publication number: 20040245560
    Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.
    Type: Application
    Filed: June 3, 2003
    Publication date: December 9, 2004
    Inventors: Marsela Pontoh, Cem Basceri, Thomas M. Graettinger
  • Publication number: 20040235242
    Abstract: The invention includes capacitor constructions comprising a layer of aluminum oxide between a high-k dielectric material and a layer comprising titanium and nitrogen. The layer comprising titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.
    Type: Application
    Filed: January 12, 2004
    Publication date: November 25, 2004
    Inventors: Cem Basceri, Thomas M. Graettinger
  • Publication number: 20040233610
    Abstract: The invention includes capacitor constructions comprising a layer of aluminum oxide between a high-k dielectric material and a layer comprising titanium and nitrogen. The layer comprising titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.
    Type: Application
    Filed: May 20, 2003
    Publication date: November 25, 2004
    Inventors: Cem Basceri, Thomas M. Graettinger
  • Publication number: 20040217409
    Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.
    Type: Application
    Filed: June 2, 2004
    Publication date: November 4, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Cem Basceri, Mark Visokay, Thomas M. Graettinger, Steven D. Cummings
  • Patent number: 6812112
    Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: November 2, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Mark Visokay, Thomas M. Graettinger, Steven D. Cummings