Patents by Inventor Thomas M. Shaw
Thomas M. Shaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8456006Abstract: The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.Type: GrantFiled: July 1, 2011Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong, Haining S. Yang
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Publication number: 20130049207Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Eric G. Liniger, Griselda Bonilla, Pak Leung, Stephan A. Cohen, Stephen M. Gates, Thomas M. Shaw
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Patent number: 8362596Abstract: A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.Type: GrantFiled: July 14, 2009Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, Jr., Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Hosadurga Shobha
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Publication number: 20130005137Abstract: A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Takeshi Nogami, Thomas M. Shaw, Andrew H. Simon, Jean E. Wynne, Chih-Chao Yang
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Patent number: 8343868Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.Type: GrantFiled: January 12, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20120329287Abstract: A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CHx)— chains wherein x is 1, 2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond.Type: ApplicationFiled: September 4, 2012Publication date: December 27, 2012Applicant: International Business Machines CorporationInventors: Stephen M. Gates, Alfred Grill, Son Nguyen, Satyanarayana V. Nitta, Thomas M. Shaw
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Publication number: 20120264292Abstract: A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.Type: ApplicationFiled: June 21, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Thomas M. Shaw
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Patent number: 8242600Abstract: A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.Type: GrantFiled: May 19, 2009Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Thomas M. Shaw
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Patent number: 8129286Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: GrantFiled: June 16, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures
Patent number: 8076756Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: GrantFiled: February 19, 2011Date of Patent: December 13, 2011Assignee: International Business Machines CorporationInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville -
Publication number: 20110260323Abstract: The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Thomas M. Shaw, Keich Kwong Hon Wong, Haining S. Yang
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Publication number: 20110193197Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MUKTA G. FAROOQ, JOHN A. GRIESEMER, WILLIAM F. LANDERS, IAN D. MELVILLE, THOMAS M. SHAW, HUILONG ZHU
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Patent number: 7972965Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.Type: GrantFiled: September 27, 2007Date of Patent: July 5, 2011Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Vincent McGahay, Thomas M. Shaw, Anthony K. Stamper, Matthew E. Colburn
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Patent number: 7973409Abstract: The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.Type: GrantFiled: January 22, 2007Date of Patent: July 5, 2011Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong, Haining S. Yang
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STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES
Publication number: 20110140245Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: ApplicationFiled: February 19, 2011Publication date: June 16, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL W. LANE, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D.W. Melville -
Patent number: 7955955Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: GrantFiled: May 10, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville
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Publication number: 20110111590Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.Type: ApplicationFiled: January 12, 2011Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7892940Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: GrantFiled: September 6, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20110012238Abstract: A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.Type: ApplicationFiled: July 14, 2009Publication date: January 20, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, JR., Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Hosadurga Shobha
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Patent number: 7847402Abstract: A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.Type: GrantFiled: February 20, 2007Date of Patent: December 7, 2010Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd, Samsung Electronics Co., LtdInventors: Darryl D. Restaino, Griselda Bonilla, Christos D. Dimitrakopoulos, Stephen M. Gates, Jae H. Kim, Michael W. Lane, Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Johnny Widodo