Patents by Inventor Thomas Neyer
Thomas Neyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119206Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.Type: ApplicationFiled: December 14, 2023Publication date: April 11, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: James Joseph VICTORY, Thomas NEYER, YunPeng XIAO, Hyeongwoo JANG, Peter DINGENEN, Vaclav VALENTA, Mehrdad BAGHAIE YAZDI, Christopher Lawrence REXER, Stanley BENCZKOWSKI, Thierry BORDIGNON, Wai Lun CHU, Roman SICKARUK
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Patent number: 11880642Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.Type: GrantFiled: September 7, 2022Date of Patent: January 23, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: James Joseph Victory, Thomas Neyer, YunPeng Xiao, Hyeongwoo Jang, Peter Dingenen, Vaclav Valenta, Mehrdad Baghaie Yazdi, Christopher Lawrence Rexer, Stanley Benczkowski, Thierry Bordignon, Wai Lun Chu, Roman Sickaruk
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Patent number: 11817478Abstract: In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.Type: GrantFiled: December 23, 2020Date of Patent: November 14, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaume Roig-Guitart, Fredrik Allerstam, Thomas Neyer, Andrei Konstantinov, Martin Domeij, Jangkwon Lim
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Publication number: 20230253460Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.Type: ApplicationFiled: April 14, 2023Publication date: August 10, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kevin Kyuheon CHO, Bongyong LEE, Kyeongseok PARK, Doojin CHOI, Thomas NEYER, Ki Min KIM
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Publication number: 20230215941Abstract: A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.Type: ApplicationFiled: March 10, 2023Publication date: July 6, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kevin Kyuheon CHO, Bongyong LEE, Kyeongseok PARK, Doojin CHOI, Thomas NEYER, James Joseph VICTORY
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Patent number: 11658214Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.Type: GrantFiled: January 12, 2021Date of Patent: May 23, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kevin Kyuheon Cho, Bongyong Lee, Kyeongseok Park, Doojin Choi, Thomas Neyer, Ki Min Kim
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Patent number: 11652027Abstract: In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.Type: GrantFiled: March 8, 2021Date of Patent: May 16, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Thomas Neyer, Herbert De Vleeschouwer, Fredrik Allerstam
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Patent number: 11605732Abstract: A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.Type: GrantFiled: November 6, 2019Date of Patent: March 14, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kevin Kyuheon Cho, Bongyong Lee, Kyeongseok Park, Doojin Choi, Thomas Neyer, James Joseph Victory
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Publication number: 20230004700Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.Type: ApplicationFiled: September 7, 2022Publication date: January 5, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: James Joseph VICTORY, Thomas NEYER, YunPeng XIAO, Hyeongwoo JANG, Peter DINGENEN, Vaclav VALENTA, Mehrdad BAGHAIE YAZDI, Christopher Lawrence REXER, Stanley BENCZKOWSKI, Thierry BORDIGNON, Wai Lun CHU, Roman SICKARUK
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Publication number: 20220359426Abstract: A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bongyong LEE, Bohee KANG, Doojin CHOI, Kyeongseok PARK, Thomas NEYER, Jeongwoo YANG
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Patent number: 11481532Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.Type: GrantFiled: October 21, 2020Date of Patent: October 25, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: James Joseph Victory, Thomas Neyer, YunPeng Xiao, Hyeongwoo Jang, Peter Dingenen, Vaclav Valenta, Tirthajyoti Sarkar, Mehrdad Baghaie Yazdi, Christopher Lawrence Rexer, Stanley Benczkowski, Thierry Bordignon, Wai Lun Chu, Roman Sickaruk
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Publication number: 20220285248Abstract: In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.Type: ApplicationFiled: March 8, 2021Publication date: September 8, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Thomas NEYER, Herbert DE VLEESCHOUWER, Fredrik ALLERSTAM
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Patent number: 11398437Abstract: A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.Type: GrantFiled: December 13, 2019Date of Patent: July 26, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bongyong Lee, Bohee Kang, Doojin Choi, Kyeongseok Park, Thomas Neyer, Jeongwoo Yang
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Publication number: 20220223691Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.Type: ApplicationFiled: January 12, 2021Publication date: July 14, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kevin Kyuheon CHO, Bongyong LEE, Kyeongseok PARK, Doojin CHOI, Thomas NEYER, Ki Min KIM
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Patent number: 11373859Abstract: Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.Type: GrantFiled: December 29, 2020Date of Patent: June 28, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Thomas Neyer, Fredrik Allerstam
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Publication number: 20220199764Abstract: In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaume ROIG-GUITART, Fredrik ALLERSTAM, Thomas NEYER, Andrei KONSTANTINOV, Martin DOMEIJ, Jangkwon LIM
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Patent number: 11152211Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.Type: GrantFiled: April 17, 2020Date of Patent: October 19, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Thomas Neyer
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Publication number: 20210183788Abstract: A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bongyong LEE, Bohee KANG, Doojin CHOI, Kyeongseok PARK, Thomas NEYER, Jeongwoo YANG
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Publication number: 20210134997Abstract: A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.Type: ApplicationFiled: November 6, 2019Publication date: May 6, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kevin Kyuheon CHO, Bongyong LEE, Kyeongseok PARK, Doojin CHOI, Thomas NEYER, James Joseph VICTORY
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Publication number: 20210117598Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.Type: ApplicationFiled: October 21, 2020Publication date: April 22, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: James Joseph VICTORY, Thomas NEYER, YunPeng XIAO, Hyeongwoo JANG, Peter DINGENEN, Vaclav VALENTA, Tirthajyoti SARKAR, Mehrdad BAGHAIE YAZDI, Christopher Lawrence REXER, Stanley BENCZKOWSKI, Thierry BORDIGNON, Wai Lun CHU, Roman SICKARUK