Patents by Inventor Thomas Neyer

Thomas Neyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210118666
    Abstract: Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.
    Type: Application
    Filed: December 29, 2020
    Publication date: April 22, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Thomas NEYER, Fredrik ALLERSTAM
  • Patent number: 10950596
    Abstract: A diode with a current sensor is disclosed. The diode includes an anode region, a cathode region, and a channel-stop region. The diode further includes a sense resistor that is connected between the channel-stop region and the cathode region. When the diode is forward biased, a sense current flows through the sense resistor that corresponds to the forward current flowing through the diode. When the diode is reverse biased, the channel-stop region helps prevent a breakdown condition in the diode.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 16, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Xiang Zeng, Xiaoli Wu, Hao Wang, Thomas Neyer, Hocheol Jang, Sungkyu Song
  • Patent number: 10896815
    Abstract: Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: January 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Thomas Neyer, Fredrik Allerstam
  • Publication number: 20200243337
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Thomas NEYER
  • Patent number: 10665458
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 26, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Thomas Neyer
  • Patent number: 10629686
    Abstract: A semiconductor power device may include a Silicon Carbide (SiC) layer having an active power device formed on a first surface thereof. An Ohmic contact layer may be formed on a second, opposing surface of the SiC layer, the Ohmic contact layer including Nickel Silicide (NiSix) with a first silicide region containing a first precipitate of non-reacted carbon disposed between the SiC layer and a second silicide region. The second silicide region may be disposed between the first silicide region and a third silicide region, and may include a mixture of a first precipitate of refractory metal carbide and a second precipitate of non-reacted carbon. The third silicide region may contain a second precipitate of refractory metal carbide. A solder metal layer may be formed on the Ohmic contact layer, with the third silicide region disposed between the second silicide region and the solder metal layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Thi Thu Phuong Pham, Kyeongseok Park, Andrei Konstantinov, Thomas Neyer
  • Publication number: 20200111776
    Abstract: A diode with a current sensor is disclosed. The diode includes an anode region, a cathode region, and a channel-stop region. The diode further includes a sense resistor that is connected between the channel-stop region and the cathode region. When the diode is forward biased, a sense current flows through the sense resistor that corresponds to the forward current flowing through the diode. When the diode is reverse biased, the channel-stop region helps prevent a breakdown condition in the diode.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Xiang ZENG, Xiaoli WU, Hao WANG, Thomas NEYER, Hocheol JANG, Sungkyu SONG
  • Publication number: 20200044031
    Abstract: A semiconductor power device may include a Silicon Carbide (SiC) layer having an active power device formed on a first surface thereof. An Ohmic contact layer may be formed on a second, opposing surface of the SiC layer, the Ohmic contact layer including Nickel Silicide (NiSix) with a first silicide region containing a first precipitate of non-reacted carbon disposed between the SiC layer and a second silicide region. The second silicide region may be disposed between the first silicide region and a third silicide region, and may include a mixture of a first precipitate of refractory metal carbide and a second precipitate of non-reacted carbon. The third silicide region may contain a second precipitate of refractory metal carbide. A solder metal layer may be formed on the Ohmic contact layer, with the third silicide region disposed between the second silicide region and the solder metal layer.
    Type: Application
    Filed: August 2, 2018
    Publication date: February 6, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thi Thu Phuong PHAM, Kyeongseok PARK, Andrei KONSTANTINOV, Thomas NEYER
  • Publication number: 20190362960
    Abstract: Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Thomas Neyer, Fredrik Allerstam
  • Publication number: 20190326117
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 24, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Thomas NEYER
  • Patent number: 10388526
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Thomas Neyer
  • Patent number: 7191085
    Abstract: In a method for testing an electric circuit, a first circuit is produced by a first process sequence. A first signal is applied to the first circuit and a signal indicating if the first circuit is defective is generated by comparing the first signal with the first circuit output signal. Then, a second circuit is produced by a second process sequence which includes incorporating at least one intentional defect structure. The first signal is applied to the second circuit and a signal is generated by comparing the first signal with the second circuit output in response to the first signal. A modified signal is applied to the second circuit, until a comparison of the modified signal and the respective response of the second circuit indicates a defective second circuit. Information about the modified signal resulting in the indication of a defective second circuit is stored.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: March 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thomas Neyer, Erwin Thalmann, Martin Versen
  • Publication number: 20060049844
    Abstract: In a method for testing an electric circuit, a first electric circuit is produced by a predetermined first process sequence. A data stream is applied to the first electric circuit and a signal being indicative if the first electric circuit is defective is generated by comparing the data stream with a data stream generated by the first electric circuit in response to the data stream. Then, a second electric circuit is produced by a predetermined second process sequence which includes incorporating intentionally at least one predetermined defect structure into the second electric circuit. The data stream is applied to the second electric circuit and a signal is generated by comparing the data stream with a data stream generated by the second electric circuit in response to the data stream.
    Type: Application
    Filed: August 29, 2005
    Publication date: March 9, 2006
    Applicant: Infineon Technologies AG
    Inventors: Thomas Neyer, Erwin Thalmann, Martin Versen
  • Publication number: 20050270865
    Abstract: The invention provides a test apparatus for testing an electronic circuit device (101) to be tested by means of a test system (100), having an interface unit (102) for connecting the circuit device (101) to be tested to the test system (100), an address decoding unit (107) for decoding external addressing data (104) input by means of the test system (100) into internal addressing data (110, 112) and for addressing memory cells of a memory cell array (108) of the circuit device (101) to be tested with the internal addressing data (110, 112), and a memory data converter (115) for converting logical memory data (106), which are fed by the test system (100), into physical memory data (114). The memory data converter (115) carries out a conversion of the logical memory data (106) fed by the test system (100) into physical memory data (114) in a manner dependent on the internal addressing data (110, 112) of the circuit device (101) to be tested.
    Type: Application
    Filed: May 26, 2005
    Publication date: December 8, 2005
    Applicant: Infineon Technologies AG
    Inventors: Sven Boldt, Manfred Moser, Erwin Thalmann, Thomas Neyer