Abstract: Radio frequency front end modules implementing coexisting time division duplexing and frequency division duplexing are provided. In one aspect, a front end system includes a time-division duplexing transmit terminal, a time-division duplexing receive terminal, a frequency division duplexing terminal, and an antenna terminal. The front end system further includes first, second, and third switches configured to selectively connect the terminals to either a node or the antenna. The front end system also includes a controller configured to provide delays between disconnecting the terminals from the antenna and connecting the terminals to the node.

Abstract: A radio-frequency module has radio-frequency input and outputs and a radio-frequency core connected between them and configured to transition between operational states. An energy management core triggers a selected transition between two of the operational states via a sequence of transitions between the plurality of operational states.

Abstract: A multi-chip module, a packaged module and a wireless device are provided. The multi-chip module comprises a plurality of layers including a first layer, a second layer and a third layer, said second layer positioned between the first layer and third layer; a low noise amplifier circuit distributed across the plurality of layers and including a first inductor in the first layer and a transistor; and a shielding plate spanning at least a portion of the second layer and overlapping at least a portion of the first inductor when viewed from a direction perpendicular to the plurality of layers, said shielding plate being electrically connected to a source terminal or emitter terminal of the transistor. The shielding plate alters a parasitic capacitance in the low noise amplifier circuit, resulting in an improved input impedance of the low noise amplifier circuit for better input matching.

Abstract: A multi-chip module, a packaged module and a wireless device are provided. The multi-chip module comprises a plurality of layers including a first layer, a second layer and a third layer, said second layer positioned between the first layer and third layer; a low noise amplifier circuit distributed across the plurality of layers and including a first inductor in the first layer, a second inductor in the third layer, and a transistor; a common ground plane spanning over at least a portion of the second layer; and a dielectric opening through the common ground plane, said dielectric opening located between the first inductor and the second inductor. The dielectric opening alters a mutual inductance in the low noise amplifier circuit, resulting in an improved input impedance of the low noise amplifier circuit for better input matching.

Abstract: Radio frequency (RF) front ends with integrated channel matching calibration are provided herein. In one aspect, a front end system includes: a plurality of front end amplification chains including transmit and receive chains for at least two radio frequency bands, each of the front end amplification chains configured to either transmit or receive radio frequency signals via one of a plurality of antennas, and each of the front end amplification chains includes an amplifier configured to receive a bias current and amplify the corresponding radio frequency signal based on the bias current, a control circuit configured to generate each of the bias currents, and a multiplexor configured to receive the bias currents and provide the bias currents to the corresponding amplifiers.

Abstract: In some embodiments, a semiconductor chip device can be manufactured by a method that includes forming a plurality of layers including a redistribution layer, such that the redistribution layer has a signal path that provides a selected electrical property with a first end electrically connected to a first node and a second end electrically connected to a second node. The method can further include coupling a semiconductor substrate with a circuit to the plurality of layers, such that the first node is electrically connected to the circuit and the second node is connectable to a location external to the semiconductor chip device.

Abstract: A front end module is presented, the FEM including a first input; a second input; an output; a low noise amplifier coupled to the first input, second input, and the output, the low noise amplifier including an analog core configured to receive an enable signal from the first input, the analog core further configured to detect edges, including rising edges and falling edges, of the enable signal and execute one or more operations based on the edges.

Abstract: Aspects and embodiments disclosed herein include a semiconductor device comprising a metal-insulator-metal capacitor having a capacitance. The metal-insulator-metal capacitor comprises a plurality of metal-insulator-metal capacitors coupled in parallel, each metal-insulator-metal capacitor of the plurality of metal-insulator-metal capacitors having a top plate, a bottom plate, and a corresponding capacitance, and a plurality of bottom contacts, at least one of the plurality of bottom contacts arranged between a pair of directly adjacent metal-insulator-metal capacitors of the plurality of metal-insulator-metal capacitors. Also disclosed are antennaplexers, electronic device modules, and electronic devices including aspects and embodiments of the semiconductor device.

Abstract: A radio-frequency module has radio-frequency input and outputs and a radio-frequency core connected between them and configured to transition between operational states. An energy management core triggers a selected transition between two of the operational states via a sequence of transitions between the plurality of operational states.

Abstract: A wireless device has an antenna and a radio frequency front-end including a variable low noise amplifier with a plurality of linearity configurations. The radio frequency front-end is configured to vary the linearity configuration corresponding to a variable status of a plurality of statuses of the wireless device.

Abstract: Radio frequency (RF) front ends with integrated channel matching calibration are provided herein. In one aspect, a front end system includes: a plurality of front end amplification chains including transmit and receive chains for at least two radio frequency bands, each of the front end amplification chains configured to either transmit or receive radio frequency signals via one of a plurality of antennas, and each of the front end amplification chains includes an amplifier configured to receive a bias current and amplify the corresponding radio frequency signal based on the bias current, a control circuit configured to generate each of the bias currents, and a multiplexor configured to receive the bias currents and provide the bias currents to the corresponding amplifiers.

Abstract: A flip-chip semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die at least first and second contact pads and a transistor including a first terminal formed within the active layer. A first portion of the first terminal falls within a footprint of the first contact pad and a second portion of the first terminal falls within a footprint of the second contact pad.

Abstract: In some embodiments, a semiconductor chip device can include a semiconductor substrate having a switching circuit with a first node, and a plurality of layers configured to support the semiconductor substrate and to provide electrical connections for the switching circuit between a second node connectable to a location external to the semiconductor chip and the first node. The plurality of layers can include a redistribution layer, and a signal path can be implemented as a part of the redistribution layer. The signal path can have a first end electrically connected to the first node and a second end electrically connected to the second node, and be configured to provide a selected inductance.

Abstract: Bias schemes for cascode power amplifiers are disclosed. In certain embodiments, a power amplifier system includes a cascode power amplifier biased by a first cascode bias voltage and that amplifies a radio frequency input signal. The power amplifier system further includes a bias voltage generation circuit including a first switch, a first cascode transmit mode bias circuit that provides the first cascode bias voltage to the cascode power amplifier through the first switch in a normal power transmit mode, a low power mode bias circuit that overrides the first cascode transmit mode bias circuit to set the first cascode bias voltage in a low power transmit mode, a second switch, and a sleep mode bias circuit that provides the first cascode bias voltage to the cascode power amplifier through the second switch in a sleep mode.

Abstract: A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.

Abstract: Programmable voltage regulators for powering multiple circuit blocks are disclosed. In certain embodiments, a front end system includes a plurality of circuit blocks, and a programmable low dropout regulator that generates a programmable regulated voltage for the plurality of circuit blocks based on a first multi-bit control signal. The programmable low dropout regulator includes a controllable frequency compensation circuit controlled by a second multi-bit control signal and operable to control a phase margin of the programmable low dropout regulator, and an overshoot control circuit controlled by a third multi-bit control signal and operable to control an overshoot of the programmable regulated voltage.

Abstract: Bias schemes for cascode power amplifiers are disclosed. In certain embodiments, a power amplifier system includes a cascode power amplifier powered by a first supply voltage and that amplifies a radio frequency input signal, and a bias circuit including a voltage regulator that generates a regulated voltage and is powered by the first supply voltage. The bias circuit further includes a bias voltage generation circuit that receives the regulated voltage and generates at least one cascode bias voltage for the cascode power amplifier, a switch that gates a second supply voltage to generate a gated supply voltage, a bias current generation circuit that controls a bias current of the cascode power amplifier and is powered by the gated supply voltage, and a gating circuit that controls the switch based on the regulated voltage and the second supply voltage.

Abstract: A system comprises a serial bus, a first module coupled to the serial bus, the first module being disposed on a first semiconductor die, including a first switch, and being configured to write to a first user identifier (USID), and a second module coupled to the serial bus, the second module being disposed on a second semiconductor die, including a second switch, and being configured to write to a second USID.

Abstract: A flip-chip semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die at least first and second contact pads and a transistor including a first terminal formed within the active layer. A first portion of the first terminal falls within a footprint of the first contact pad and a second portion of the first terminal falls within a footprint of the second contact pad.

Abstract: A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.