Patents by Inventor Thomas Obkircher
Thomas Obkircher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210218433Abstract: Cascode power amplifier bias circuits suitable for operating across multiple power supply domains are provided. In certain embodiments, a power amplifier system includes a cascode power amplifier and a multi-domain bias circuit that generates at least a first cascode bias voltage for the cascode power amplifier. The multi-domain bias circuit includes a coarse regulator that generates a regulated voltage based on a power supply voltage that is operable with multiple voltage levels associated with different power supply domains, a bandgap reference circuit that is powered by the regulated voltage and outputs a bandgap reference voltage, a bias voltage generator that generates multiple selectable bias voltages based on the bandgap reference voltage, and a bias voltage selector that chooses the first cascode bias voltage from amongst the selectable bias voltages.Type: ApplicationFiled: December 29, 2020Publication date: July 15, 2021Inventors: Bang Li Liang, Thomas Obkircher, Guillaume Alexandre Blin
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Publication number: 20210210429Abstract: A flip-chip semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die at least first and second contact pads and a transistor including a first terminal formed within the active layer. A first portion of the first terminal falls within a footprint of the first contact pad and a second portion of the first terminal falls within a footprint of the second contact pad.Type: ApplicationFiled: December 30, 2020Publication date: July 8, 2021Inventors: Yang Liu, Yong Lee, Thomas Obkircher
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Publication number: 20210210415Abstract: A semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die includes at least one contact pad and a transistor including a first terminal formed within the active layer. A conduction path can include a plurality of first conduction path portions extending between the first terminal and the at least one contact pad and residing within a footprint of the at least one contact pad.Type: ApplicationFiled: December 30, 2020Publication date: July 8, 2021Inventors: Yang Liu, Yong Lee, Thomas Obkircher
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Publication number: 20210211107Abstract: A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.Type: ApplicationFiled: December 29, 2020Publication date: July 8, 2021Inventors: Yang Liu, Yong Lee, Thomas Obkircher, William J. Domino
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Publication number: 20210173807Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Inventors: Thomas Obkircher, Guillaume Alexandre Blin, James Henry Ross, Bryan J. Roll
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Patent number: 10998862Abstract: Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.Type: GrantFiled: September 23, 2019Date of Patent: May 4, 2021Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Bang Li Liang, Thomas Obkircher, Adrian John Bergsma, Peter Harris Robert Popplewell
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Patent number: 10963418Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.Type: GrantFiled: August 28, 2019Date of Patent: March 30, 2021Assignee: Skyworks Solutions, Inc.Inventors: Thomas Obkircher, Guillaume Alexandre Blin, James Henry Ross, Bryan J. Roll
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Patent number: 10812030Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.Type: GrantFiled: August 27, 2019Date of Patent: October 20, 2020Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Peihua Ye, Patrick Marcus Naraine, Adrian John Bergsma, Peter Harris Robert Popplewell, Thomas Obkircher
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Publication number: 20200057746Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.Type: ApplicationFiled: August 28, 2019Publication date: February 20, 2020Inventors: Thomas Obkircher, Guillaume Alexandre Blin, James Henry Ross, Bryan J. Roll
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Patent number: 10560202Abstract: Systems and methods are provided for reducing the effects of an impedance mismatch between a communications system and a shared communications medium. A communication system, such as a transceiver within a cable modem, switches between various operating modes including a transmit mode, a receive mode, and a standby mode. The standby mode may be used while the transceiver is in an idle state between modes, such as while changing an amplifier gain states in between transmissions. While transitioning between modes, the impedance presented by the communications system can temporarily fluctuate causing unwanted signal reflections to propagate out of the communications system and on to the shared medium. Circuitry within the communications system, such as transmission circuitry including an adjustable attenuator, may be placed into a hybrid attenuation-isolation mode during the transition causing the magnitude of any unwanted signal reflections to be attenuated and reducing the impact on the shared medium.Type: GrantFiled: February 22, 2019Date of Patent: February 11, 2020Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Adrian John Bergsma, Peihua Ye, Thomas Obkircher, Peter Harris Robert Popplewell, Gregory Edward Babcock, William J. Domino
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Patent number: 10554188Abstract: Systems and methods for suppressing transient outputs from an amplifier system are provided. An amplifier having a plurality of bias levels may be controlled to initiate a change in the level of a bias signal provided to the amplifier. The level of the bias signal is ramped from an initial bias level to a final bias level over numerous steps. The steps include at least one step in which the level of the bias signal is between the initial bias level and the final bias level. An amplifier system having multiple stages may be controlled to enable each stage and selectively couple each stage in a sequence that couples an output stage to an output terminal at the completion of the sequence.Type: GrantFiled: November 9, 2017Date of Patent: February 4, 2020Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Adrian John Bergsma, Thomas Obkircher, Peihua Ye, Bang Li Liang, Peter Harris Robert Popplewell, William J. Domino
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Publication number: 20200021249Abstract: Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.Type: ApplicationFiled: September 23, 2019Publication date: January 16, 2020Inventors: Bang Li Liang, Thomas Obkircher, Adrian John Bergsma, Peter Harris Robert Popplewell
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Publication number: 20190386624Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Inventors: Peihua Ye, Patrick Marcus Naraine, Adrian John Bergsma, Peter Harris Robert Popplewell, Thomas Obkircher
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Publication number: 20190334493Abstract: Amplifier systems and methods are provided that include a fixed gain amplification stage coupled to an adjustable attenuation stage further coupled to a variable gain amplification stage. A controller controls an amount of attenuation provided by the adjustable attenuation stage and an amount of gain provided by the variable gain amplification stage to maintain any of various noise, efficiency, and/or linearity requirements of the amplifier system.Type: ApplicationFiled: July 10, 2019Publication date: October 31, 2019Inventors: William J. Domino, Thomas Obkircher, Adrian John Bergsma, Peihua Ye
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Patent number: 10461700Abstract: Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.Type: GrantFiled: November 9, 2017Date of Patent: October 29, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Bang Li Liang, Thomas Obkircher, Adrian John Bergsma, Peter Harris Robert Popplewell
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Patent number: 10437774Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.Type: GrantFiled: January 22, 2018Date of Patent: October 8, 2019Assignee: Skyworks Solutions, Inc.Inventors: Thomas Obkircher, Guillaume Alexandre Blin, James Henry Ross, Bryan J. Roll
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Patent number: 10439576Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.Type: GrantFiled: November 9, 2017Date of Patent: October 8, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Peihua Ye, Patrick Marcus Naraine, Adrian John Bergsma, Peter Harris Robert Popplewell, Thomas Obkircher
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Patent number: 10396737Abstract: Amplifier systems and methods are provided that include a fixed gain amplification stage coupled to an adjustable attenuation stage further coupled to a variable gain amplification stage. A controller controls an amount of attenuation provided by the adjustable attenuation stage and an amount of gain provided by the variable gain amplification stage to maintain any of various noise, efficiency, and/or linearity requirements of the amplifier system.Type: GrantFiled: November 9, 2017Date of Patent: August 27, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: William J. Domino, Thomas Obkircher, Adrian John Bergsma, Peihua Ye
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Publication number: 20190190623Abstract: Systems and methods are provided for reducing the effects of an impedance mismatch between a communications system and a shared communications medium. A communication system, such as a transceiver within a cable modem, switches between various operating modes including a transmit mode, a receive mode, and a standby mode. The standby mode may be used while the transceiver is in an idle state between modes, such as while changing an amplifier gain states in between transmissions. While transitioning between modes, the impedance presented by the communications system can temporarily fluctuate causing unwanted signal reflections to propagate out of the communications system and on to the shared medium. Circuitry within the communications system, such as transmission circuitry including an adjustable attenuator, may be placed into a hybrid attenuation-isolation mode during the transition causing the magnitude of any unwanted signal reflections to be attenuated and reducing the impact on the shared medium.Type: ApplicationFiled: February 22, 2019Publication date: June 20, 2019Inventors: Adrian John Bergsma, Peihua Ye, Thomas Obkircher, Peter Harris Robert Popplewell, Gregory Edward Babcock, William J. Domino
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Patent number: 10256921Abstract: Systems and methods are provided for reducing the effects of an impedance mismatch between a communications system and a shared communications medium. A communication system, such as a transceiver within a cable modem, switches between various operating modes including a transmit mode, a receive mode, and a standby mode. The standby mode may be used while the transceiver is in an idle state between modes, such as while changing an amplifier gain states in between transmissions. While transitioning between modes, the impedance presented by the communications system can temporarily fluctuate causing unwanted signal reflections to propagate out of the communications system and on to the shared medium. Circuitry within the communications system, such as transmission circuitry including an adjustable attenuator, may be placed into a hybrid attenuation-isolation mode during the transition causing the magnitude of any unwanted signal reflections to be attenuated and reducing the impact on the shared medium.Type: GrantFiled: November 9, 2017Date of Patent: April 9, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Adrian John Bergsma, Peihua Ye, Thomas Obkircher, Peter Harris Robert Popplewell, Gregory Edward Babcock, William J. Domino