Patents by Inventor Thomas P. Duffy
Thomas P. Duffy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120101342Abstract: A pediatric tissue illuminator includes a semi-rigid lighting head removably connected to a powered base unit for illuminating an infant's tissues while stabilizing a limb for venipuncture. The lighting head includes a series of LEDs and is placed behind an infant's arm, thereby directing light therethrough for enhanced viewing. A printed circuit board in the lighting head routes electrical conductors to the LEDs. A translucent soft covering is disposed between the printed circuit board and the infant's body. The base unit includes a control circuit for varying the application of electrical power to the lighting head via an electrical cable. The arm board/light head is inexpensive enough to be disposable. Alternatively, a re-useable light head may be used with disposable semi-rigid housings.Type: ApplicationFiled: October 19, 2011Publication date: April 26, 2012Inventors: Thomas P. Duffy, Gerald T. Harder, Kevin Mori
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Publication number: 20120101343Abstract: A trans-illumination device includes at least first and second sets of LEDs of two or more different colors arranged in a light head placed against a patient's skin. The LEDs are mounted to a printed circuit board in the light head. An electronic control circuit is coupled to the light head by an electrical cable to selectively operate the LEDs in two or more user-selected modes, with the ability to adjust the relative intensities of the different colors to best suit the physiology of the patient. The light head may have a U-shape to surround an area of interest while providing ready access thereto. The light head may be used with a disposable, detachable cover having lenses for directing light from the LEDs into the patient's tissues.Type: ApplicationFiled: October 19, 2011Publication date: April 26, 2012Inventors: Thomas P. Duffy, Gerald T. Harder, Kevin Mori
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Patent number: 7002249Abstract: A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires.Type: GrantFiled: November 12, 2002Date of Patent: February 21, 2006Assignee: Primarion, Inc.Inventors: Thomas P. Duffy, John Ryan Goodfellow, Robert T. Carroll, Kevin J. Cote, Sampath K. V. Karikalan, Suresh Golwalkar
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Patent number: 6965502Abstract: The present invention provides a power regulation system and method with high speed signal settling capabilities for providing rapid active transient response to a microelectronic device. An active transient response system includes a power supply configured to receive external and/or internal signals indicating the occurrence of transient load conditions and to respond to the transient load conditions based on one or more of these signals. The system may further include a transient suppressor configured for early detection of transients, assisting in transient suppression, and early signaling of transient activity to the power supply. The system provides rapid recovery to steady state operation from the active transient response mode by using a digital compensator to quickly modifying the duty cycle and provide a voltage offset proportional to the transient microprocessor load step. Recovery is further improved by current rephasing techniques.Type: GrantFiled: March 22, 2002Date of Patent: November 15, 2005Assignee: Primarion, Inc.Inventors: Thomas P. Duffy, Ryan Goodfellow, Malay Trivedi, Kevin Mori, Benjamim Tang
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Patent number: 6795009Abstract: Currents flowing in the various channels within a voltage regulator module (VRM) are suitably converted to digital equivalents that can be processed to control each module in a modular power supply. Functions that may be digitally implemented include current balancing between channels, current sharing between various modules in a power supply, and/or the like. By monitoring the current provided on each channel within a module, for example, a controller can determine an average current for the channels, which in turn can be used to identify and compensate for over- or under-production in any particular channel. Active voltage positioning techniques and overload protection may also be implemented using digital techniques.Type: GrantFiled: September 9, 2002Date of Patent: September 21, 2004Assignee: Primarion, Inc.Inventors: Thomas P. Duffy, Malay Trivedi, Kevin Mori
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Publication number: 20040104456Abstract: A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires.Type: ApplicationFiled: November 12, 2002Publication date: June 3, 2004Inventors: Thomas P. Duffy, John Ryan Goodfellow, Robert T. Carroll, Kevin J. Cote, Sampath K.V. Karikalan, Suresh Golwalkar
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Publication number: 20040046535Abstract: Currents flowing in the various channels within a voltage regulator module (VRM) are suitably converted to digital equivalents that can be processed to control each module in a modular power supply. Functions that may be digitally implemented include current balancing between channels, current sharing between various modules in a power supply, and/or the like. By monitoring the current provided on each channel within a module, for example, a controller can determine an average current for the channels, which in turn can be used to identify and compensate for over- or under-production in any particular channel. Active voltage positioning techniques and overload protection may also be implemented using digital techniques.Type: ApplicationFiled: September 9, 2002Publication date: March 11, 2004Applicant: Primarion Inc., Tempe, ArizonaInventors: Thomas P. Duffy, Malay Trivedi, Kevin Mori
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Patent number: 6674320Abstract: A control system, method and apparatus is provided for an orthogonally variable inductor. A method and apparatus is also provided for voltage regulation. Regulation is provided without the use of Silicon devices, such as FET's, in the output current path. Efficient voltage regulation is provided via varying the inductance of a device in the output current path, and alternatively via varying the inductance and duty cycle. An orthogonal inductive device is provided to vary the inductance in the output current path. The orthogonal inductive device is an external H field device, a series method orthogonal flux device, or a combined core device. Furthermore, a variable inductor is also provided in filters, amplifiers, and oscillators.Type: GrantFiled: October 16, 2001Date of Patent: January 6, 2004Assignee: Primarion, Inc.Inventors: Thomas P. Duffy, Yi Zhang, Malay Trivedi
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Patent number: 6563294Abstract: A highly phased power regulation (converter) system having an improved control feature is provided. A controller, such as a digital signal processor or microprocessor, receives digital information from a plurality of power conversion blocks and transmits control commands in response to the information. The controller is able to change the mode of operation of the system and/or re-phase the power blocks to accommodate a dynamic load requirement, occasions of high transient response or detection of a fault. In one embodiment, a microprocessor receives digital information and converted power from one or more power blocks. In this manner, the microprocessor is able to receive feedback on its own operation. The controller is also able to anticipate and predict conditions by analyzing precursor data. In this manner, the controller is able to modify the system as needed in anticipation of the forthcoming event.Type: GrantFiled: April 1, 2002Date of Patent: May 13, 2003Assignee: Primarion, Inc.Inventors: Thomas P. Duffy, Ryan Goodfellow, David Susak
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Publication number: 20020171985Abstract: The present invention provides a power regulation system and method with high speed signal settling capabilities for providing rapid active transient response to a microelectronic device. An active transient response system includes a power supply configured to receive external and/or internal signals indicating the occurrence of transient load conditions and to respond to the transient load conditions based on one or more of these signals. The system may further include a transient suppressor configured for early detection of transients, assisting in transient suppression, and early signaling of transient activity to the power supply.Type: ApplicationFiled: March 22, 2002Publication date: November 21, 2002Inventors: Thomas P. Duffy, Ryan Goodfellow, Malay Trivedi, Kevin Mori, Benjamim Tang
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Publication number: 20020118001Abstract: A highly phased power regulation (converter) system having an improved control feature is provided. A controller, such as a digital signal processor or microprocessor, receives digital information from a plurality of power conversion blocks and transmits control commands in response to the information. The controller is able to change the mode of operation of the system and/or re-phase the power blocks to accommodate a dynamic load requirement, occasions of high transient response or detection of a fault. In one embodiment, a microprocessor receives digital information and converted power from one or more power blocks. In this manner, the microprocessor is able to receive feedback on its own operation. The controller is also able to anticipate and predict conditions by analyzing precursor data. In this manner, the controller is able to modify the system as needed in anticipation of the forthcoming event.Type: ApplicationFiled: April 1, 2002Publication date: August 29, 2002Inventors: Thomas P. Duffy, Ryan Goodfellow, David Susak
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Publication number: 20020060621Abstract: A control system, method and apparatus is provided for an orthogonally variable inductor. A method and apparatus is also provided for rectifying an AC power supply for a DC load. DC voltage regulation is also provided. Rectification and regulation is provided without the use of Silicon devices, such as FET's, in the output current path. Efficient voltage rectification and regulation is provided via varying the inductance of a device in the output current path, and alternatively via varying the inductance and duty cycle. An orthogonal inductive rectifier is provided to vary the inductance in the output current path. The orthogonal inductive rectifier is an external H field device, a series method orthogonal flux device, or a combined core device. Furthermore, a variable inductor is also provided in filters, amplifiers, and oscillators.Type: ApplicationFiled: October 16, 2001Publication date: May 23, 2002Inventors: Thomas P. Duffy, Yi Zhang, Malay Trivedi
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Publication number: 20020047768Abstract: An improved magnetic structure suitable for electronic applications is disclosed. The magnetic structure may be formed on or within a substrate such as a printed circuit board by forming a layer of magnetic material, pattering the layer of magnetic material, and etching the layer to form the magnetic structure. Various insulating layers and/or conductive layers may then be formed over the magnetic structures as part of the substrate. Inductors suitable for use in power supplies may be formed using the magnetic structures of the present invention.Type: ApplicationFiled: October 10, 2001Publication date: April 25, 2002Inventor: Thomas P. Duffy
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Patent number: 5620782Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.Type: GrantFiled: June 2, 1995Date of Patent: April 15, 1997Assignee: International Business Machines CorporationInventors: Charles R. Davis, Thomas P. Duffy, Steven L. Hanakovic, Howard L. Heck, John T. Kolias, John S. Kresge, David N. Light, Ajit K. Trivedi
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Patent number: 5599747Abstract: A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.Type: GrantFiled: June 27, 1995Date of Patent: February 4, 1997Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, David E. Houser, Gerald W. Jones, Jeffrey McKeveny, Kenneth L. Potter
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Patent number: 5578796Abstract: According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening.Type: GrantFiled: June 6, 1995Date of Patent: November 26, 1996Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, Gerry A. Hackett, Jeffrey McKeveny
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Patent number: 5566448Abstract: A method of forming an I/C chip mounting module, and for mounting an I/C chip thereon, is disclosed. A rigid cap and substrate are provided. A bottomed cavity is routed in the cap, and the substrate has circuitry formed thereon. The cap and substrate are laminated together with bond pads, which connect to the circuitry being disposed in the cavity. After circuitization of the exposed surface of the cap and drilling and plating of vias, the material of the cap overlying the cavity is removed to expose the bond pads. Thereafter, an I/C chip is connect to the pads.Type: GrantFiled: June 6, 1995Date of Patent: October 22, 1996Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, Jeffrey A. Knight, James P. Walsh
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Patent number: 5542175Abstract: According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening.Type: GrantFiled: December 20, 1994Date of Patent: August 6, 1996Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, Gerry A. Hackett, Jeffrey McKeveny
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Patent number: 5509196Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.Type: GrantFiled: September 21, 1994Date of Patent: April 23, 1996Assignee: International Business Machines CorporationInventors: Charles R. Davis, Thomas P. Duffy, Steven L. Hanakovic, Howard L. Heck, John T. Kolias, John S. Kresge, David N. Light, Ajit K. Trivedi
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Patent number: 5460921Abstract: The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured.Type: GrantFiled: September 8, 1993Date of Patent: October 24, 1995Assignee: International Business Machines CorporationInventors: Douglas A. Cywar, Charles R. Davis, Thomas P. Duffy, Frank D. Egitto, Paul J. Hart, Gerald W. Jones, Edward McLeskey