Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Abstract: Due to size and cost, it becomes advantageous for integrated circuit (IC) manufacturers to use “single-ended” (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit board) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit board. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads.

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

Abstract: A method and structure is provided for constructing elastomeric pin arrays using solder interconnects and a non-conductive medium. Pin to pin interconnects are constructed using a solder connection through a non-conductive medium. This structure eliminates the need for PCB structures as the medium, reducing manufacturing cost. In another embodiment one or more elastomeric columns extend through holes or openings in the non conductive medium. The elastomeric columns are fixed securely within the holes preferably with adhesive material. Compression stops are provided on both sides of each elastomeric column for both the upper and bottom surfaces of the non conductive medium.

Abstract: A method and structure for improving signal integrity probing. A coaxial or a microcoaxial cable is threaded through an optional alignment substrate where the cable is used to support or align the cable or an array of cables. A conductive elastomer is placed on a cable or a microcoaxial cable to improve signal integrity probing.

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

Abstract: A shuttle board relay is provided that is scalable to a specific pitch or routing density. The shuttle board relay provides a path with different sets of electrical components that allows this via by allowing the integration of components and other types of customization. The shuttle board relay provides a minimally disruptive path to the signal. This minimizes loss and signal distortion, isolation and crosstalk are a function of pitch. Since pitch can be set, grounds included, etc., a design may be fully optimized for low cross talk.

Abstract: A method and a structure with multiple implementations is provided that depends on the specific need, for placing (embedding) a serial loopback circuit of known design in a printed circuit board directly beneath the device under test. Micro-vias and traces connect components including transmitter components (TX) and receiver components (RX) that are formed into a loopback circuit for connection to a device under test (DUT). The connection is accomplished by a coupling capacitor with a shortest possible electrical length approximating a straight line between said components and said DUT and said distance is a length of said short straight line times a square root of 2 so that said receiver components are beneath the DUT.

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

Abstract: Due to size and cost, it becomes advantageous for integrated circuit (IC) manufacturers to use “single-ended” (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit board) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit board. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground.

Abstract: A method and electrical interconnect structure internal to a printed circuit board for the purposes of creating a reliable, high performing connection method between embedded component terminals, signal traces and or power/ground planes which may occupy the same vertical space as the embedded components, such as a capacitor or resistor. Further easing the assembly and reliability through the manufacturing process of said embedded component structures. In one structure castellated drilled, plated vias connect the trace or plane within the printed circuit board to the electrical terminals of the embedded component using a permanent and highly conductive attach material. In another structure, the trace or plane connect by selective side-wall plating, which surrounds the electrical terminal of the component.

Abstract: A method and structure is provided for constructing elastomeric pin arrays using solder interconnects and a non-conductive medium. Pin to pin interconnects are constructed using a solder connection through a non-conductive medium. This structure eliminates the need for PCB structures as the medium, reducing manufacturing cost. In another embodiment a non conductive medium has holes therein and serves as a compression stop. One or more first elastomeric column is formed on an upper side of a conductive disc. The conductive disc is fixedly adhered to a pad located on an underside of the non conductive medium aligned so that the one or more first elastomeric column extends through said holes of the non conductive medium. One or more second elastomeric column is formed on an underside or bottom of the conductive medium or disc.

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

Abstract: A shuttle board relay is provided that is scalable to a specific pitch or routing density. The shuttle board relay provides a path with different sets of electrical components that allows this via by allowing the integration of components and other types of customization. The shuttle board relay provides a minimally disruptive path to the signal. This minimizes loss and signal distortion, isolation and crosstalk are a function of pitch. Since pitch can be set, grounds included, etc., a design may be fully optimized for low cross talk.

Abstract: A method and structure for improving signal integrity probing. A coaxial or a microcoaxial cable is threaded through an optional alignment substrate where the cable is used to support or align the cable or an array of cables. A conductive elastomer is placed on a cable or a microcoaxial cable to improve signal integrity probing.

Abstract: The present disclosure relates to reducing unwanted RF noise in a printed circuit board (PCB) containing an RF device. An isolation filter is embedded in a PCB containing an RDF device. By placing the isolation filter as close as possible to the RF device in order to dramatically reduce unwanted RF noise due to unavoidable coupling between Vias and planes in the PCB structure.