Abstract: A method and apparatus for an omnidirectional helically arrayed antenna are described. In accordance with at least one embodiment, a horizontally polarized omnidirectional helically arrayed antenna is provided. In accordance with at least one embodiment, an antenna comprises a helical array of coaxial transmission line radiating elements coupled to one another successively by phase changing couplings. In accordance with at least one embodiment, the antenna is configured to provide an omnidirectional radiation pattern and a polarization dominated by a magnetic field vector component parallel to an axis of the helical array and an electric field vector component perpendicular to the axis of the helical array. In accordance with at least one embodiment, an electrical length of each of the coaxial transmission line radiating elements is an odd integer multiple of a half wavelength in the coaxial medium with a pitch in the range of 0.35 wavelength to 0.50 wavelength.

Abstract: One embodiment of an electrostatic protection diode in an integrated circuit includes a base area having at least two bends therein.

Abstract: One embodiment of an electrostatic protection diode in an integrated circuit includes a base area having at least two bends therein.

Abstract: One embodiment of an electrostatic protection diode in an integrated circuit includes a base area having at least two bends therein.

Abstract: Embodiments of circuits and systems for a harmonic tuning network coupled with a radio frequency (RF) push-pull power amplifier to terminate both second- and third-harmonic energies are disclosed. Other embodiments may also be described and claimed.

Abstract: Embodiments of methods, apparatus, devices and/or systems associated with bipolar junction transistor are disclosed.

Abstract: Embodiments of a microelectronic device including laminate baluns are generally described herein. A microelectronic device may include a laminate structure including a plurality of laminate layers, a first balun element disposed in the laminate structure, and a second balun element disposed in the laminate structure, wherein at least a portion of the first balun element is situated over the second balun element. Other embodiments may be described and claimed.

Abstract: An interconnect path configured for use in RFICs and configured to reduce inductance at the input of an array of cells, and also at the output of the array of cells. According to one preferred embodiment of the present invention, a multi-layered interconnect formed by at least two metal layers separated by dielectric medium is provided. The metal layers are closely spaced and separated by a desirable dielectric to achieve an interconnect having a characteristic inductance (Zo) that is much lower than typical microstrip transmission lines formed by a metal trace over the semiconductor substrate or a dielectric stack that includes the semiconductor substrate. The low Zo line provides much less inductance per unit length.

Abstract: A power amplifier circuit includes two amplifier subsections and delay elements coupled in parallel. An input received by the second amplifier subsection is a delayed version of the input received by the first amplifier subsection. The output of the first amplifier subsection is delayed such that the delayed output of the first amplifier subsection is in phase with the output of the second amplifier subsection. For low output power operation, only the first amplifier subsection is enabled. For high output power operation, both the first and the second amplifier subsections are enabled. The first and the second amplifier subsections operate as saturated amplifiers. A first variable output power control signal controls the output power of the first amplifier subsection, and a second variable output power control signal controls the output power of the second amplifier subsection.

Abstract: A bias control system for the radio frequency power amplifiers that includes a current source, a mirror current, and a bias voltage.

Abstract: A bias control system for the radio frequency power amplifiers that includes a current source, a mirror current, and a bias voltage.

Abstract: One embodiment of an electrostatic protection diode in an integrated circuit includes a base area having at least two bends therein.

Abstract: A switched distributed power amplifier includes an amplifier stage that includes a first amplifier subsection and a second amplifier subsection, both including one or more field effect transistors (FETs). Each FET in the first amplifier subsection is coupled to a radio frequency (RF) input terminal. Each FET in the second amplifier subsection is coupled to the RF input terminal through an input delay element, which includes a first inductor, a first capacitance associated with gates of the FETs in the first amplifier subsection, a second capacitance associated with gates of the FETs in the second amplifier subsection, and a third capacitance associated with a capacitor coupled to the RF input terminal. The input delay element is designed such that the sum of the first and third capacitances is equal to the second capacitance. A shunt switch prevents the second amplifier subsection from turning on during a low power mode.

Abstract: Described herein are representative embodiments of amplifiers having selectable power output while maintaining low power consumption. In certain exemplary embodiments, the amplifiers are operated as linear power amplifiers, such as may be used in wireless communication systems. According to one exemplary embodiment, a circuit is described comprising a control system configured to operate the circuit in at least a first mode and a second mode. The circuit of this embodiment further includes a first amplifier section configured to amplify at least a portion of an input signal and produce a first amplified signal on a first signal path in the first mode of operation, a second amplifier section configured to amplify at least a portion of an input signal and produce a second amplified signal on a second signal path in the second mode of operation, and an impedance inverter having an input coupled to the first and second signal paths.

Abstract: A power amplifier stage has a first amplifier subsection and a second amplifier subsection coupled in a parallel configuration. The first amplifier subsection receives a signal to be amplified and the second amplifier subsection receives the signal to be amplified via a first delay line. The amplified output signal of the first amplifier subsection is passed through a second impedance inverter and is combined with the amplified output signal from the second amplifier subsection. In a low power mode, the first amplifier subsection operates as a linear amplifier and the second subsection is biased off. In a high power mode, both the first and second amplifier subsections operate as linear amplifiers. Selecting the impedances of the second delay element and the first amplifier to be equal is essential for high power mode operation and greatly improves the amplifier efficiency in the low power mode.

Abstract: An interconnect path configured for use in RFICs and configured to reduce inductance at the input of an array of cells, and also at the output of the array of cells. According to one preferred embodiment of the present invention, a multi-layered interconnect formed by at least two metal layers separated by dielectric medium is provided. The metal layers are closely spaced and separated by a desirable dielectric to achieve an interconnect having a characteristic inductance (Zo) that is much lower than typical microstrip transmission lines formed by a metal trace over the semiconductor substrate or a dielectric stack that includes the semiconductor substrate. The low Zo line provides much less inductance per unit length, and also provides an increase in the parasitic capacitance per unit length.

Abstract: An amplifier bias system. The amplifier bias system includes a battery voltage supply coupled with an amplifier transistor to be biased; an output node coupled with a gate of the amplifier transistor; and a current source coupled with the battery voltage supply, wherein the current source provides a current to a node in response to the battery voltage supply. The amplifier bias system further includes a first transistor coupled between the battery voltage supply and the output node, the first transistor having a gate coupled with the first node; a second transistor coupled with the first node, the second transistor having a gate coupled with the output node; and a current load coupled with the output node.

Abstract: An RF transmitter provides both GSM and EDGE capability by implementing collector voltage control over the power transistor(s) in a power amplifier. During EDGE mode, linear base-biasing a power amplifier (PA) allows collector control to provide either saturated mode PA operation (during ramp up/ramp down) or linear mode PA operation (during data burst). Collector control can therefore be used to provide the accurate ramp up and ramp down profiles required for both GSM and EDGE burst output signals, and can also be used to set the level of the constant envelope data burst of a GSM burst output signal, while linear mode PA operation can provide the non-constant envelope EDGE data burst. A variable gain amplifier is used to adjust the input signal to the power amplifier such that the desired transmission level is achieved.

Abstract: A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered reference DC bias voltage lowers amplifier gain and output power, thus protecting the amplifier.

Abstract: A circuit includes a transmission line transformer coupled between an input and output port. An inductor may be selectively coupled into the ground return path of the transmission line transformer to alter the impedance transformation provided between the input and output ports.