Abstract: A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during the low power operating mode, and enabled during the high power operating mode. Because neither the first nor second amplifier output stage is operated in an extremely low quiescent current state, the linearity of the power amplifier is maintained for both high power and low power operating modes.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.

Abstract: A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during the low power operating mode, and enabled during the high power operating mode. Because neither the first nor second amplifier output stage is operated in an extremely low quiescent current state, the linearity of the power amplifier is maintained for both high power and low power operating modes.

Abstract: A transmission line element is formed in an integrated circuit chip. The transmission line element includes a plurality of parallel conductors, with each conductor including a plurality of electrically connected transmission lines. At least two of the transmission lines of each conductor are in different ones of plural metal layers of the integrated circuit chip. The metal layers are separated by at least one dielectric layer. Each transmission line in each conductor is edge-coupled to a transmission line of another of the conductors, and broadside-coupled to a transmission line of another of the conductors. The transmission line element can be used, for example, to fabricate various types of balanced and unbalanced transformers.

Abstract: A bias control circuit generates a bias control current that is proportional to temperature. The bias control current is drawn from a first node of a bias circuit. The first node of the bias circuit is also configured to receive a relatively large first current that is also proportional to temperature. A bias current is also drawn from the first node, wherein the bias current is equal to the difference between the relatively large first current and the bias control current. The temperature sensitivities of the bias control current and the relatively large first current are matched, such that the bias control current is relatively insensitive to changes in temperature.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.

Abstract: A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered reference DC bias voltage lowers amplifier gain and output power, thus protecting the amplifier.

Abstract: A combination edge- and broadside-coupled transmission line element formed in an integrated circuit chip, using semiconductor processes, in a stack of metal layers separated by dielectric layers. Each of the metal layers includes a number of transmission lines. Interconnects between the transmission lines are formed at predetermined locations, each interconnect electrically connecting together a group of the transmission lines to form a conductor. The efficiency of the coupling between the lines in the different conductor is increased by positioning the lines such that both edge and broadside-coupling is realized. For example, at least one of the transmission lines in one of the conductors is positioned either above or below a transmission line in the other conductor to achieve broadside-coupling and laterally adjacent to another transmission line in the other conductor to achieve edge-coupling.

Abstract: A combination edge- and broadside-coupled transmission line element formed in an integrated circuit chip, using semiconductor processes, in a stack of metal layers separated by dielectric layers. Each of the metal layers includes a number of transmission lines. Interconnects between the transmission lines are formed at predetermined locations, each interconnect electrically connecting together a group of the transmission lines to form a conductor. The efficiency of the coupling between the lines in the different conductor is increased by positioning the lines such that both edge- and broadside-coupling is realized. For example, at least one of the transmission lines in one of the conductors is positioned either above or below a transmission line in the other conductor to achieve broadside-coupling and laterally adjacent to another transmission line in the other conductor to achieve edge-coupling.

Abstract: A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered reference DC bias voltage lowers amplifier gain and output power, thus protecting the amplifier.

Abstract: A power amplifier circuit includes two amplifier subsections and delay elements coupled in parallel. An input received by the second amplifier subsection is a delayed version of the input received by the first amplifier subsection. The output of the first amplifier subsection is delayed such that the delayed output of the first amplifier subsection is in phase with the output of the second amplifier subsection. For low output power operation, only the first amplifier subsection is enabled. For high output power operation, both the first and the second amplifier subsections are enabled. The first and the second amplifier subsections operate as saturated amplifiers. A first variable output power control signal controls the output power of the first amplifier subsection, and a second variable output power control signal controls the output power of the second amplifier subsection.

Abstract: A power amplifier stage has a first amplifier subsection and a second amplifier subsection coupled in a parallel configuration. The first amplifier subsection receives a signal to be amplified and the second amplifier subsection receives the signal to be amplified via a first delay line. The amplified output signal of the first amplifier subsection is passed through a second impedance inverter and is combined with the amplified output signal from the second amplifier subsection. In a low power mode, the first amplifier subsection operates as a linear amplifier and the second subsection is biased off. In a high power mode, both the first and second amplifier subsections operate as linear amplifiers. Selecting the impedances of the second delay element and the first amplifier to be equal is essential for high power mode operation and greatly improves the amplifier efficiency in the low power mode.

Abstract: Base ballast resistors used to control thermal runaway are each bypassed with a series-resonant inductor and capacitor pair. In some embodiments each inductor and capacitor pair is unique. In other embodiments a common inductor is used for each inductor and capacitor pair.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.

Abstract: A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during the low power operating mode, and enabled during the high power operating mode. Because neither the first nor second amplifier output stage is operated in an extremely low quiescent current state, the linearity of the power amplifier is maintained for both high power and low power operating modes.

Abstract: A bias control circuit generates a bias control current that is proportional to temperature. The bias control current is drawn from a first node of a bias circuit. The first node of the bias circuit is also configured to receive a relatively large first current that is also proportional to temperature. A bias current is also drawn from the first node, wherein the bias current is equal to the difference between the relatively large first current and the bias control current. The temperature sensitivities of the bias control current and the relatively large first current are matched, such that the bias control current is relatively insensitive to changes in temperature.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.

Abstract: A combination edge- and broadside-coupled transmission line element formed in an integrated circuit chip, using semiconductor processes, in a stack of metal layers separated by dielectric layers. Each of the metal layers includes a number of transmission lines. Interconnects between the transmission lines are formed at predetermined locations, each interconnect electrically connecting together a group of the transmission lines to form a conductor. The efficiency of the coupling between the lines in the different conductor is increased by positioning the lines such that both edge- and broadside-coupling is realized. For example, at least one of the transmission lines in one of the conductors is positioned either above or below a transmission line in the other conductor to achieve broadside-coupling and laterally adjacent to another transmission line in the other conductor to achieve edge-coupling.

Abstract: An improved amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an amplifier transistor that has a base terminal connected to receive an input signal. The amplifier circuit also includes a reference voltage source that generates a reference voltage at a reference voltage output node. A local bias circuit provides a bias voltage to the base terminal of the amplifier transistor. The local bias circuit includes a first transistor that has an emitter terminal coupled to the reference voltage output node, a collector terminal coupled to a supply voltage node, and a base terminal connected to the collector terminal. The local bias circuit also includes a second transistor that has a base terminal coupled to the base terminal of the first transistor, a collector terminal coupled to the supply voltage node, and an emitter terminal coupled to the base terminal of the amplifier transistor.

Abstract: A set of clamping diodes between terminals of a transistor acting as a power amplifier is configured to allow overvoltage at the output terminal of the transistor to travel through those clamping diodes to provide feedback used by the transistor for gain control.