Abstract: A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion.

Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.

Abstract: This invention provides novel fuel cell electrodes and catalysts comprising a series of catalytically active thin-film metal alloys with low platinum concentration supported on nanostructured materials (nanoparticles). Processing of the electrodes and catalysts can include electrodeposition methods, and high-pressure coating techniques. In certain embodiments, an integrated gas-diffusion/electrode/catalyst layer can be prepared by processing catalyst thin films and nanoparticles into gas-diffusion media such as Toray or SGL carbon fiber papers. The catalysts can be placed in contact with an electrolyte membrane for PEM fuel cell applications.

Abstract: This invention provides novel fuel cell electrodes and catalysts comprising a series of catalytically active thin-film metal alloys with low platinum concentration supported on nanostructured materials (nanoparticles). Processing of the electrodes and catalysts can include electrodeposition methods, and high-pressure coating techniques. In certain embodiments, an integrated gas-diffusion/electrode/catalyst layer can be prepared by processing catalyst thin films and nanoparticles into gas-diffusion media such as Toray or SGL carbon fiber papers. The catalysts can be placed in contact with an electrolyte membrane for PEM fuel cell applications.

Abstract: Illuminated footwear including a translucent sole insert housing LEDs, preferably of different colors which may be combined to produce a wide array of colors is provided. The heel similarly includes a translucent insert and includes an interior mirror material and an illumination source. An on/off switch in the toe of the footwear is connected in a circuit with a replaceable battery, a control processor and the LEDs. The control processor includes logic that may dim, strobe, or shut off all or some of the LEDs. In operation, when the device is activated, the LEDs are illuminated. The light from the individual LEDs is blended and reflected by the interior mirror materials in an outward direction from the shoe. The translucent material in the sole and heel of the shoe allows the blended light to pass through to create a pleasing visual effect.

Abstract: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 ?), pure (impurities<1 at. %), AlOx films with improved breakdown strength (9–10 MV/cm) with a commercially feasible throughput.

Abstract: Atomic layer deposition systems and methods are disclosed utilizing a multi-wafer sequential processing chamber. The process gases are sequentially rotated among the wafer stations to deposit a portion of a total deposition thickness on each wafer at each station. A rapid rotary switching of the process gases eliminates having to divert the process gases to a system vent and provides for atomic layer film growth sufficient for high-volume production applications. Conventional chemical vapor deposition can also be performed concurrently with atomic layer deposition within the multi-wafer sequential processing chamber.

Abstract: A method of conductive copper lines in a semiconductor device is provided. A dielectric structure having a surface with recessed features formed therein is provided. A ruthenium oxide layer is deposited over the surface of the dielectric structure. A ruthenium oxide and metallic ruthenium bilayer is formed from the ruthenium oxide layer. Copper conductive lines are formed in the recessed features.

Abstract: A method and system for fabricating a device on a substrate with a process gas, such as with chemical vapor deposition. A reaction chamber and support chuck cooperate to form a low conductance configuration for axisymetric process gas flow over the substrate and to form a high conductance configuration for enhanced evacuation of residual process gas from the reaction chamber upon completion of the process. A dual conductance chuck has an indented region that aligns with the exhaust port of the reaction chamber to restrict process gas flow in the low conductance configuration, and that moves distal a showerhead and the exhaust port to provide reduced restriction of process gas flow for reaction chamber evacuation. The chuck includes thermal control for enhancing film deposition on the substrate and for reducing residual film deposition on the chuck. An evacuation opening in the housing provides independent evacuation of residual gas from the housing.

Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Abstract: A method and system for fabricating a device on a substrate with a process gas, such as with chemical vapor deposition. A reaction chamber and support chuck cooperate to form a low conductance configuration for axisymetric process gas flow over the substrate and to form a high conductance configuration for enhanced evacuation of residual process gas from the reaction chamber upon completion of the process. A dual conductance chuck has an indented region that aligns with the exhaust port of the reaction chamber to restrict process gas flow in the low conductance configuration, and that moves distal a showerhead and the exhaust port to provide reduced restriction of process gas flow for reaction chamber evacuation. The chuck includes thermal control for enhancing film deposition on the substrate and for reducing residual film deposition on the chuck. An evacuation opening in the housing provides independent evacuation of residual gas from the housing.

Abstract: A method and system for fabricating a device on a substrate with a process gas, such as with chemical vapor deposition. A reaction chamber and support chuck cooperate to form a low conductance configuration for axisymetric process gas flow over the substrate and to form a high conductance configuration for enhanced evacuation of residual process gas from the reaction chamber upon completion of the process. A dual conductance chuck has an indented region that aligns with the exhaust port of the reaction chamber to restrict process gas flow in the low conductance configuration, and that moves distal a showerhead and the exhaust port to provide reduced restriction of process gas flow for reaction chamber evacuation. The chuck includes thermal control for enhancing film deposition on the substrate and for reducing residual film deposition on the chuck. An evacuation opening in the housing provides independent evacuation of residual gas from the housing.

Abstract: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 Å), pure (impurities <1 at. %), AlOx films with improved breakdown strength (9-10 MV/cm) with a commercially feasible throughput.

Abstract: Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput.

Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Abstract: A method for chemical-vapor deposition of a material film adds precursor decomposition by-product to the precursor flow to suppress premature gas-phase precursor decomposition and improve process repeatability and film quality. In one embodiment, CVD cobalt films are deposited with carbonyl precursors with reduced premature gas-phase reaction and particulate generation by the addition of excess carbon monoxide to the process chamber comprising the precursor flow. The addition of carbon monoxide not only suppresses gas-phase reaction but also improves cobalt film purity. The addition of excess carbon monoxide to CVD cobalt precursor flow provides repeatable deposition of glue and nucleation layers to support CVD copper, and is extendable to the deposition of high purity CVD cobalt for other applications and with other precursors, and also extendable for CVD CoSi2 films and other cobalt-containing applications.

Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Abstract: Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput.