Abstract: This disclosure relates to a select class of porous adsorbent, metal-organic frameworks (MOFs) capable of adsorbing carbon dioxide, their manufacturing, applications, and methods of use. Specifically, this disclosure relates to the solvo(hydro)thermal synthesis of a family of metal-organic frameworks, and their subsequent processing and transformation into material forms suitable for use in acid gas separations. More specifically, this disclosure relates to the preparation and recovery of MOFs at multiple scales of production, demonstrating the suitability and robustness of the materials thus obtained by the disclosed synthetic route and post-synthetic manipulation employed to tailor the materials for use in a variety of commercial acid gas separation systems, with improved performances, recyclability, and reuse characteristics.

Abstract: According to an aspect, an apparatus may include a media streaming device including electronic circuitry configured to receive media content wirelessly from a media content source, and an output cord segment having a first end portion integrally coupled to a structure of the media streaming device, and a second end portion configured to be coupled to a receiving device, where the electronic circuitry is further configured to transmit the received media content through the output cord segment to the receiving device. The apparatus may include a power cord segment having a first end portion configured to be coupled to the media streaming device, and a second end portion configured to be coupled to a power source.

Abstract: An airbag inflator includes a lower pressure vessel supporting an initiator assembly, a booster can centrally mounted in the lower pressure vessel and secured to the initiator assembly, and an energetics canister secured over the booster can such that the energetics canister is positioned radially between the lower pressure vessel and the booster can. An energetics cover encloses a circumferential space between the booster can and the energetics canister. A flow diverter closes the booster can and includes inlet vent openings downstream of the energetics cover. An upper pressure vessel positioned over the flow diverter and engaging the lower pressure vessel includes an exit orifice sealed with a rupturable membrane. A manifold is secured over the upper pressure vessel. The inflator increases combustion efficiency and lowers gaseous effluents.

Abstract: Hinged safety gates and methods for controlling access to an elevated work surface are disclosed. The hinged safety gate can include a gate frame and a retainer assembly. The gate frame can have a distal upright member, an upper cross-arm, and a lower cross-arm. The upper cross-arm can have an upper cross-arm height (or vertical dimension), and the lower cross-arm can have a lower cross-arm height. The hinged safety gate can have a retainer assembly that is configured to be attached to a proximal end of the gate frame and to hingedly couple the gate frame to a stationary vertical surface, permitting the gate frame to swing between an open and a closed position. Some embodiments satisfy various spatial safety requirements with only two cross-arms. Some embodiments are horizontally adjustable in two different manners to accommodate a range of access area widths.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: The present invention provides ISVD polypeptide derivatives capable of binding coagulation Factor IX(a) and Factor X(a) which are highly potent and provide a sufficiently long half-life such to allow for effective subcutaneous—as well as peroral administration. The ISVD polypeptides derivatives disclosed herein are thus suitable for treatment of haemophilia A, haemophilia A with inhibitors and acquired haemophilia A by various routes of administration including subcutaneous and peroral administration.

Abstract: A method for the fractionation of reclaimed polymer in at least one solvent in a process for purifying reclaimed polymers plastic recycling to increase their use in secondary applications. The reclaimed polymer is dissolved in a solvent within a reactor vessel having a stack of perforated discs which are oscillated. The linear motion of the stack speeds up dissolution time to minutes rather than hours and the required polymer to solvent ratio can be increased to 0.3 to 10% wt addition. Temperature and time effects are used to fractionate polymers of differing molecular weights to provide purified and graded plastics for secondary use at a commercially viable scale.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.

Abstract: A hardware representation of a fixed logic circuit is derived for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: A method to dissolve a polymer in a solvent in a process for the removal of additives in plastics, in which the polymer and solvent are combined in a reactor vessel having a stack of perforated discs which are oscillated. The linear motion of the stack speeds up dissolution time to minutes rather than hours and the required polymer to solvent ratio can be increased to 0.3 to 10% wt addition. The reactor vessel can be heated with pressure remaining at atmospheric. The method lends itself to commercial scale processing with reactor vessels of 1,000 litres and greater.

Abstract: The present invention relates to a polypeptide comprising a piggyBac transposase or a fragment or a derivative thereof having transposase function comprising at least one amino acid substitution. Further, the present invention relates to a transposable element comprising a piggyBac or piggyBac-like left repeat sequence and left internal repeat sequence, wherein the left internal repeat sequence comprises at least one nucleotide modification. Furthermore, the present invention relates to a kit comprising the above transposase and/or transposable element. In addition, the present invention relates to a targeting system comprising the above transposase and/or transposable element.

Abstract: A computer-implemented method for deriving a hardware representation of a fixed logic circuit for performing division of an input x by a divisor selectable from a plurality of divisors, where x is an m-bit integer, includes normalising each of the plurality of divisors to form a plurality of multipliers; forming a summation array arranged to multiply the input x by any one of the plurality of multipliers; truncating the summation array by discarding all columns less significant than the kth column of the summation array below the position of a binary point, where k=[log2m]; determining a corrective constant in dependence on the maximum sum of the partial products discarded from the summation array for at least one of the multipliers; and generating a hardware representation of a fixed logic circuit implementing the truncated summation array including the corrective constant.

Abstract: A fixed logic circuit for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode. Fixed logic hardware is derived comprising an addition array configured to operate on canonical signed digit (CSD) forms of binary values (a CSD array) so as to form an approximation of a multiplication of an input x [m?1:0] by a rational p/q. A truncated summation array of a finite sequence of most significant bits of an infinite CSD expansion of the rational p/q operating on the bits of the input x satisfies ? high - ? low < 1 q . Registers define a plurality of corrective constants for a respective plurality of rounding modes, and selection logic selects the respective corrective constant for that rounding mode in dependence on a rounding mode in which the truncated summation array is to operate.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.

Abstract: A fixed logic circuit configured to determine one or more of the most significant bits of the multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2m?1, and m is a positive integer, the fixed logic circuit comprising: division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation: ? 2 i ? x q ? where i is the minimum positive value which satisfies: 2 i ( 2 i ? mod ? a ) > a * ( 2 m - 1 ) + 1 ? q = ? 2 i a ? and output logic configured to provide the one or more most significant bits of the result of the division operation as the respective one or more most significant bits of the multiplication operation a*x.

Abstract: A fixed logic circuit configured to perform a multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2m?1, and m is a positive integer. The fixed logic circuit includes division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation: ?2ix/q? where q,i are selected such that: a*x=?2ix/q? Multiplication logic determines a predetermined number of one or more least significant bits of the result of the multiplication operation a*x; and output logic combines the predetermined number of one or more most significant bits of the result of the division operation with the predetermined number of one or more least significant bits of the result of the multiplication operation so as to provide an output for the multiplication operation a*x.

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 / d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.