Abstract: The present invention relates to a polypeptide comprising a piggyBac transposase or a fragment or a derivative thereof having transposase function comprising at least one amino acid substitution. Further, the present invention relates to a transposable element comprising a piggyBac or piggyBac-like left repeat sequence and left internal repeat sequence, wherein the left internal repeat sequence comprises at least one nucleotide modification. Furthermore, the present invention relates to a kit comprising the above transposase and/or transposable element. In addition, the present invention relates to a targeting system comprising the above transposase and/or transposable element.

Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 / d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 / d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing a non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a selection of bits of the binary classification dataset and sort its received selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.

Abstract: A binary logic circuit for determining y=x mod (2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: A process for the extraction of one or more colour pigments from waste plastic in which a waste plastic feedstock is mixed with a solvent in a reactor having a shearing mechanism and the solvent is separated out and recycled in the process. The shearing mechanism provides high shear, high contact mixing so as to move the pigment to the surface of the plastic for contact with the solvent to give efficient colour pigment removal. Embodiments of reactors with shearing mechanisms are described. Environmentally friendly solvents are also described. The process gives highly sought after natural recyclate at a commercial scale.

Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Abstract: A sensor plaster (116) for the transcutaneous measurement of an organ function, more particularly of a kidney function, is proposed. The sensor plaster (116) comprises at least one flexible carrier element (134) having at least one adhesive surface (138) which can be stuck onto a body surface. Furthermore, the sensor plaster (116) comprises at least one radiation source, more particularly a light source (142), wherein the radiation source is designed to irradiate the body surface with at least one interrogation light (162). Furthermore, the sensor plaster (116) comprises at least one detector (146) designed to detect at least one response light (176) incident from the direction of the body surface.

Abstract: In order to produce a transport bag for transporting liquid samples, in particular blood, urine, tissue samples, or the like, two film layers made of plastic are placed one on top of the other and joined to one another in such a manner that an interior space is formed between the film layers. Before the two film layers are placed one on top of the other, a liquid or viscous carrier material into which absorber particles are or will be mixed is applied to at least one of the film layers. Subsequently, the carrier material with the absorber particles is dried and/or cooled. Preferably, the carrier material is sprayed or spattered or printed or knife coated or brushed onto the film layer.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: A method for the fractionation of reclaimed polymer in at least one solvent in a process for purifying reclaimed polymers plastic recycling to increase their use in secondary applications. The reclaimed polymer is dissolved in a solvent within a reactor vessel having a stack of perforated discs which are oscillated. The linear motion of the stack speeds up dissolution time to minutes rather than hours and the required polymer to solvent ratio can be increased to 0.3 to 10% wt addition. Temperature and time effects are used to fractionate polymers of differing molecular weights to provide purified and graded plastics for secondary use at a commercially viable scale.

Abstract: A hardware representation of a fixed logic circuit is derived for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: A method to dissolve a polymer in a solvent in a process for the removal of additives in plastics, in which the polymer and solvent are combined in a reactor vessel having a stack of perforated discs which are oscillated. The linear motion of the stack speeds up dissolution time to minutes rather than hours and the required polymer to solvent ratio can be increased to 0.3 to 10% wt addition. The reactor vessel can be heated with pressure remaining at atmospheric. The method lends itself to commercial scale processing with reactor vessels of 1,000 litres and greater.

Abstract: The present invention relates to a polypeptide comprising a piggyBac transposase or a fragment or a derivative thereof having transposase function comprising at least one amino acid substitution. Further, the present invention relates to a transposable element comprising a piggyBac or piggyBac-like left repeat sequence and left internal repeat sequence, wherein the left internal repeat sequence comprises at least one nucleotide modification. Furthermore, the present invention relates to a kit comprising the above transposase and/or transposable element. In addition, the present invention relates to a targeting system comprising the above transposase and/or transposable element.

Abstract: A fixed logic circuit for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode. Fixed logic hardware is derived comprising an addition array configured to operate on canonical signed digit (CSD) forms of binary values (a CSD array) so as to form an approximation of a multiplication of an input x [m?1:0] by a rational p/q. A truncated summation array of a finite sequence of most significant bits of an infinite CSD expansion of the rational p/q operating on the bits of the input x satisfies ? high - ? low < 1 q . Registers define a plurality of corrective constants for a respective plurality of rounding modes, and selection logic selects the respective corrective constant for that rounding mode in dependence on a rounding mode in which the truncated summation array is to operate.

Abstract: A computer-implemented method for deriving a hardware representation of a fixed logic circuit for performing division of an input x by a divisor selectable from a plurality of divisors, where x is an m-bit integer, includes normalising each of the plurality of divisors to form a plurality of multipliers; forming a summation array arranged to multiply the input x by any one of the plurality of multipliers; truncating the summation array by discarding all columns less significant than the kth column of the summation array below the position of a binary point, where k=[log2m]; determining a corrective constant in dependence on the maximum sum of the partial products discarded from the summation array for at least one of the multipliers; and generating a hardware representation of a fixed logic circuit implementing the truncated summation array including the corrective constant.