Patents by Inventor Thomas Rose

Thomas Rose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11531522
    Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 20, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Thomas Rose, Robert McKemey
  • Publication number: 20220391205
    Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 / d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.
    Type: Application
    Filed: August 4, 2022
    Publication date: December 8, 2022
    Inventors: Thomas Rose, Max Freiburghaus, Robert McKemey
  • Publication number: 20220365755
    Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 17, 2022
    Inventor: Thomas Rose
  • Patent number: 11429389
    Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: August 30, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Simon Nield, Thomas Rose
  • Patent number: 11422802
    Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 ? / ? d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 23, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Thomas Rose, Max Freiburghaus, Robert McKemey
  • Patent number: 11409500
    Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: August 9, 2022
    Assignee: Imagination Technologies Limited
    Inventor: Thomas Rose
  • Publication number: 20220214772
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.
    Type: Application
    Filed: December 13, 2021
    Publication date: July 7, 2022
    Inventors: Joel Grayson Webber, Stephanie Jill Brubaker, Hollis Bruce Johnson, Jr., Ian Thomas Rose, Scott Mitchell Voigt, Jaime Michael Yap, Joshua Calvin Teague
  • Publication number: 20220156203
    Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 19, 2022
    Inventors: Luca Iuliano, Simon Nield, Thomas Rose
  • Publication number: 20220090142
    Abstract: The present invention relates to a polypeptide comprising a transposase and at least one heterologous chromatin reader element (CRE). Further, the present invention relates to a polynucleotide encoding the polypeptide. Furthermore, the present invention relates to a vector comprising the polynucleotide. In addition, the present invention relates to a kit comprising a transposase and at least one heterologous chromatin reader element (CRE).
    Type: Application
    Filed: February 13, 2019
    Publication date: March 24, 2022
    Inventors: Sven Krügener, Thomas Rose, Volker Sandig, Karsten Winkler
  • Patent number: 11249925
    Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 15, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Luca Iuliano, Simon Nield, Thomas Rose
  • Publication number: 20220040889
    Abstract: A process for the extraction of one or more colour pigments from waste plastic in which a waste plastic feedstock is mixed with a solvent in a reactor having a shearing mechanism and the solvent is separated out and recycled in the process. The shearing mechanism provides high shear, high contact mixing so as to move the pigment to the surface of the plastic for contact with the solvent to give efficient colour pigment removal. Embodiments of reactors with shearing mechanisms are described. Environmentally friendly solvents are also described. The process gives highly sought after natural recyclate at a commercial scale.
    Type: Application
    Filed: September 16, 2019
    Publication date: February 10, 2022
    Inventors: Thomas Rose, Steven Burns, Emmeline Aves, Andrew West
  • Publication number: 20220010345
    Abstract: The present invention relates to a method for producing a composition containing isomaltulose from a substrate containing sucrose comprising the steps of: a) contacting the substrate containing sucrose with a particulate carrier-immobilized sucrose isomerase biomass and b) obtaining a composition containing isomaltulose, characterized in that the median particle size d(0.5) of the carrier-immobilized sucrose isomerase biomass is from 370 to 550 ?m. The carrier can be an alginate or a polyvinyl alcohol carrier.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 13, 2022
    Inventors: Wolfgang Wach, Thomas Rose
  • Patent number: 11199939
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: December 14, 2021
    Assignee: FullStory, Inc.
    Inventors: Joel Grayson Webber, Stephanie Jill Brubaker, Hollis Bruce Johnson, Jr., Ian Thomas Rose, Scott Mitchell Voigt, Jaime Michael Yap, Joshua Calvin Teague
  • Publication number: 20210081178
    Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Inventor: Thomas Rose
  • Publication number: 20210081205
    Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Inventors: Simon Nield, Thomas Rose
  • Publication number: 20210055836
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Joel Grayson Webber, Stephanie Jill Brubaker, Hollis Bruce Johnson, JR., Ian Thomas Rose, Scott Mitchell Voigt, Jaime Michael Yap, Joshua Calvin Teague
  • Publication number: 20210052207
    Abstract: A sensor plaster (116) for the transcutaneous measurement of an organ function, more particularly of a kidney function, is proposed. The sensor plaster (116) comprises at least one flexible carrier element (134) having at least one adhesive surface (138) which can be stuck onto a body surface. Furthermore, the sensor plaster (116) comprises at least one radiation source, more particularly a light source (142), wherein the radiation source is designed to irradiate the body surface with at least one interrogation light (162). Furthermore, the sensor plaster (116) comprises at least one detector (146) designed to detect at least one response light (176) incident from the direction of the body surface.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Norbert Gretz, Johannes Pill, Daniel Schock-Kusch, Thomas Walter, Jürgen Hesser, Maliha Sadick, Felix Eickemeyer, Jae Hyung Hwang, Christian Schildknecht, Soichi Watanabe, Wolfgang Wach, Thomas Rose
  • Patent number: 10877732
    Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: December 29, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Thomas Rose
  • Patent number: 10877760
    Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: December 29, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Simon Nield, Thomas Rose
  • Patent number: 10838571
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: November 17, 2020
    Assignee: FullStory, Inc.
    Inventors: Joel Grayson Webber, Stephanie Jill Brubaker, Hollis Bruce Johnson, Jr., Ian Thomas Rose, Scott Mitchell Voigt, Jaime Michael Yap, Joshua Calvin Teague