Abstract: The present disclosure generally provides compounds that antagonize certain T2R taste receptors, including related uses, methods, and compositions for the reduction of bitter taste and/or the enhancement of sweet taste. In certain aspects, the disclosure provides flavored articles or flavored compositions comprising such compounds, as well as uses of such compounds to reduce the bitter taste and/or enhance the sweet taste of such flavored articles or flavored compositions.

Abstract: A filtration system has a filter element with a filtration membrane, a feed inlet and a concentrate outlet on a first side of the membrane and a permeate outlet on a second side of the membrane. A feed line with a feed shutoff valve is in fluid communication with the feed inlet, and a concentrate return line with a concentrate shutoff valve is in fluid communication with the concentrate outlet. A feed pump is in fluid communication with the feed inlet via the feed line and the feed shutoff valve, and a backwash pump is in fluid communication with the permeate outlet. In a priming phase of a backwash operation, the feed shutoff valve and the concentrate shutoff valve are closed and the backwash supply is operable to deliver fluid to the filtration element and equalize pressure between the first side and the second side of the filtration membrane.

Abstract: An integrated circuit supplied by a rail-to-rail power supply voltage includes a multi-level stack voltage generator configured to partition the rail-to-rail power supply voltage into one or more reduced supply voltages each having a voltage value between positive and negative power supply voltages of the rail-to-rail power supply. The reduced supply voltages and the positive and negative power supply voltages being configured in series to form a stack of circuit layers. The integrated circuit further includes a core circuit including core circuit units coupled in a circuit layer or coupled between two or more circuit layers. Each core circuit unit is coupled to at least one of the reduced supply voltages. The core circuit units are coupled in the stack of circuit layers to form a serial connection of core circuit units between the positive power supply voltage and the negative power supply voltage.

Abstract: An integrated circuit supplied by a rail-to-rail power supply voltage includes a multi-level stack voltage generator configured to partition the rail-to-rail power supply voltage into one or more reduced supply voltages each having a voltage value between positive and negative power supply voltages of the rail-to-rail power supply. The reduced supply voltages and the positive and negative power supply voltages being configured in series to form a stack of circuit layers. The integrated circuit further includes a core circuit including core circuit units coupled in a circuit layer or coupled between two or more circuit layers. Each core circuit unit is coupled to at least one of the reduced supply voltages. The core circuit units are coupled in the stack of circuit layers to form a serial connection of core circuit units between the positive power supply voltage and the negative power supply voltage.

Abstract: A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

Abstract: A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

Abstract: A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

Abstract: A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

Abstract: A laser bias control and monitoring circuit receives a monitor diode current on an input node and generate a bias current for a laser diode on an output node where the monitor diode current flows into (positive polarity) or out of (negative polarity) the input node. The laser bias control and monitoring circuit includes a polarity independent current sensing circuit configured to receive the monitor diode current in either positive or negative polarity and to generate a normalized output current having a magnitude proportional to a magnitude of the monitor diode current. In this manner, the laser bias control and monitoring circuit can be used with laser diode and monitor diode combination in either the common anode or the common cathode configuration, or with the monitor diode current being provided from the anode or cathode of the monitor diode. No reprogramming or reconfiguration of the circuit is required.

Abstract: A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

Abstract: A laser bias control and monitoring circuit receives a monitor diode current on an input node and generate a bias current for a laser diode on an output node where the monitor diode current flows into (positive polarity) or out of (negative polarity) the input node. The laser bias control and monitoring circuit includes a polarity independent current sensing circuit configured to receive the monitor diode current in either positive or negative polarity and to generate a normalized output current having a magnitude proportional to a magnitude of the monitor diode current. In this manner, the laser bias control and monitoring circuit can be used with laser diode and monitor diode combination in either the common anode or the common cathode configuration, or with the monitor diode current being provided from the anode or cathode of the monitor diode. No reprogramming or reconfiguration of the circuit is required.

Abstract: An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output.

Abstract: A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

Abstract: A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream.

Abstract: A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier.

Abstract: An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output.

Abstract: A receiver converts an analog signal, derived from light pulses in a GPON fiber optic system, to clean digital electrical signals. A photodetector and transimpedance amplifier (TIA) convert the light pulses to analog electrical signals. A reset signal generated by a media access controller (MAC) in the GPON system signifies the start of a new burst of data. The receiver has a switchable low pass filter that establishes the threshold voltage for determining whether the analog signal is a logical 1 or a logical 0. At the very start of a new burst, the low pass filter has a fast time constant to quickly establish the threshold voltage for the burst. At a later time during the burst, the low pass filter is switched to have a slow time constant to create a relatively stable threshold voltage.

Abstract: A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle.

Abstract: A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter.

Abstract: Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.