Abstract: A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter.

Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

Abstract: A laser driver circuit includes a laser APC circuit receiving a monitor current indicative of the average optical output power of a laser diode and providing a bias adjust signal for adjusting a bias current for the laser diode. The laser APC circuit includes a first non-linear impedance circuit receiving the monitor current and generating a first voltage using a first non-linear current-to-voltage transfer function, a second non-linear impedance circuit receiving a reference current and generating a second voltage and being implemented using the same or a scaled version of the first non-linear current-to-voltage transfer function, and a comparator for comparing the first voltage with the second voltage and providing the bias adjust signal indicative of the difference between the first and second voltages. The first non-linear current-to-voltage transfer function has difference resistance portions for increasing the dynamic range of the current-to-voltage conversion.

Abstract: An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.

Abstract: A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle.

Abstract: A laser driver circuit includes a laser APC circuit receiving a monitor current indicative of the average optical output power of a laser diode and providing a bias adjust signal for adjusting a bias current for the laser diode. The laser APC circuit includes a first non-linear impedance circuit receiving the monitor current and generating a first voltage using a first non-linear current-to-voltage transfer function, a second non-linear impedance circuit receiving a reference current and generating a second voltage and being implemented using the same or a scaled version of the first non-linear current-to-voltage transfer function, and a comparator for comparing the first voltage with the second voltage and providing the bias adjust signal indicative of the difference between the first and second voltages. The first non-linear current-to-voltage transfer function has difference resistance portions for increasing the dynamic range of the current-to-voltage conversion.

Abstract: A receiver converts an analog signal, derived from light pulses in a GPON fiber optic system, to clean digital electrical signals. A photodetector and transimpedance amplifier (TIA) convert the light pulses to analog electrical signals. A reset signal generated by a media access controller (MAC) in the GPON system signifies the start of a new burst of data. The receiver has a switchable low pass filter that establishes the threshold voltage for determining whether the analog signal is a logical 1 or a logical 0. At the very start of a new burst, the low pass filter has a fast time constant to quickly establish the threshold voltage for the burst. At a later time during the burst, the low pass filter is switched to have a slow time constant to create a relatively stable threshold voltage.

Abstract: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

Abstract: An interface system couples a fixed impedance device to a receiver for transmitting data signals at different data rates at different times. The interface system includes elements that are connected to provide different time constants of responsiveness to data signals of higher and lower data rates without distorting the data signals beyond usability.

Abstract: An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.

Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

Abstract: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

Abstract: An isolation resistor is inserted in series between a current source and the emitters of bipolar switching transistors in a differential amplifier. The switching transistors may also be MOSFETs. The in-rush current through the resistor, due to a parasitic or added capacitance, creates a certain increased voltage drop across the resistor, reducing dv/dt and thus reducing the transient in-rush current into the capacitor. This results in reduced waveform distortion. Such an isolation resistor between a current carrying terminal of a switching bipolar transistor and a current source may be used in various applications, including an emitter follower.

Abstract: A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to prevent the transistor from saturating. The clamp diodes can also be used to adjust the output voltage of the gate to ensure downstream transistors can be fully turned off.

Abstract: Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.

Abstract: Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.

Abstract: A digital memory characterized by a plurality of memory cells arranged into a matrix having rows and columns; a row activation circuit for concurrently activating all of the rows of the matrix; and column activation means for concurrently applying either a reset signal or a preset signal to the columns of the matrix. The column activation circuit can include a plurality of digital switches coupled to reset and preset lines associated with each column of the matrix; and reset/preset logic which control the digital switches to selectively couple the reset and preset lines to a constant current source. A complementary, multi-emitter flip-flop memory cell is formed on a semiconductor substrate and includes "riser" portions.

Abstract: A tag buffer having built-in testing capabilities is disclosed. In a single-chip, integrated-circuit design which includes a SRAM, a parity generator and checker, and a comparator, a method and capability of testing the functionality of the SRAM and parity components is defined. For an embodiment in which the SRAM component includes a redundancy scheme for replacing a defective memory array row, a test for determining whether a redundant row has been used is also provided.

Abstract: The circuit derives Vbep, the base-emitter voltage of a saturated PNP transistor, from the PNP portion of a four-layer (PNPN) silicon-controlled rectifier (SCR) so as to exactly match the characteristics of the PNP portion of an SCR against which the reference voltage is to be compared. The operating point of the SCR in the voltage-reference circuit is adjusted and controlled to duplicate the operating conditions in the circuit to be measured. The voltage between the end layers of the SCR includes the sum of Vbep and Vcen, the collector-emitter drop of the NPN portion of the SCR. The circuit processes this voltage to remove the Vcen term, providing an output voltage which depends upon Vbep.

Abstract: A new and improved write and read control circuit for semiconductor memories is provided that comprises a first pair of transistors having their emitter terminals coupled to a current source, a base terminal of a first of the first pair being disposed for receiving data to be written in the array and a base terminal of a second of the first pair being coupled to a first reference potential, and each of the first pair of transistors having collector terminals; a second pair of transistors having their collector terminals coupled to a second reference potential, the base terminal of a first of the second pair being coupled to the collector terminal of the first of the first pair of transistors and the base terminal of a second of the second pair being coupled to the collector terminal of a second of the first pair, the emitter terminal of the first of the second pair being coupled to a second current source and forming a first output of the circuit, and the emitter terminal of the second of the second pair bein