Patents by Inventor Thomas Schafbauer

Thomas Schafbauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RAISED EXTENSION STRUCTURE FOR HIGH PERFORMANCE CMOS
    Publication number: 20030166323
    Abstract: In a process of fabricating on a substrate a CMOS semiconductor device having a gate electrode, a raised source, and a raised drain, the improvement comprising further incorporating a raised extension, comprising:
    Type: Application
    Filed: March 1, 2002
    Publication date: September 4, 2003
    Applicant: Infineon Technologies North America Corp.
    Inventors: Dirk Vietzke, Thomas Schafbauer, James Brighten, Birgit Von Ehrenwall
  • Method and structure for shallow trench isolation
    Patent number: 6472301
    Abstract: A method (see e.g., FIG. 4) of fabricating a semiconductor device includes forming a trench 12 in a semiconductor body 10. A dielectric layer 26 is formed within the trench 12. Dielectric layer 26 lines the sidewall and, possibly, the bottom portions of the trench 12 in a manner where the thickness of the dielectric 26s at the sidewall is greater than the thickness of the dielectric 26b at the bottom. A dopant 28 can then be implanted into the semiconductor body beneath the trench.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: October 29, 2002
    Assignee: Infineon Technologies AG
    Inventors: Chuan Lin, Thomas Schafbauer, Paul Wensley
  • Apparatus for processing a substrate wafer and method for operating same
    Patent number: 5998767
    Abstract: An apparatus for processing a substrate wafer wherein the apparatus includes a reaction chamber, a wafer holder intended to hold the substrate wafer, and a susceptor. A temperature sensor, preferably a thermocouple with two junctions, is provided for measuring the difference between the temperatures at the site of the susceptor and at a site between the susceptor and the substrate wafer.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: December 7, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alfred Kersch, Thomas Schafbauer