Patents by Inventor Thomas W. Dyer

Thomas W. Dyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9455186
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20160260674
    Abstract: Upon a wafer, integrated circuit (IC) chips are separated by a kerf that includes a through kerf via (TKV). The chips are removed from the wafer and separated from each other by removing the TKV. The TKV may be formed simultaneous or subsequent to formation of a through via (TSV) within an active inner region of each IC chip. The TKV reduces wasted area of the wafer allowing for more IC chips to be included thereupon. Further, the TKV allows for IC chips included in the wafer to differ in perimeter geometry.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 8, 2016
    Inventors: Bradley P. Jones, Thomas W. Dyer
  • Patent number: 9431535
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 9406560
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9385038
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: July 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9276111
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Publication number: 20150325531
    Abstract: A semiconductor device includes an active inner region and a crack stop region. The active inner region includes a semiconductor substrate, an integrated circuit (IC) device layer formed upon the semiconductor substrate, and a wiring layer formed upon the IC device layer. The IC device layer includes an integrated circuit device and the wiring layer includes wiring in electrical contact with the integrated circuit device. The crack stop region limits the propagation of cracks and delamination into the active inner region and includes semiconductor material surrounding a crack stop via (CSV) extending through the crack stop region. A lower surface of the CSV may be coplanar with lower surfaces of the crack stop layer and the active inner layer. An upper surface of the CSV may be coplanar with upper surfaces of the crack stop layer and the active inner layer.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Bradley P. Jones
  • Patent number: 9157980
    Abstract: A test layout structure including a first series of parallel metal lines in a first level, and a first series of contact structures in a second level, the second level being positioned above the first level, the first series of contact structures being positioned at known increments, where the increments are in a direction perpendicular to a length of the first series of parallel metal lines, and where one or more of the first series of contact structures is in electrical contact with one or more of the first series of parallel metal lines.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Stephen E. Greco
  • Publication number: 20150255342
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20150255397
    Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 10, 2015
    Inventors: Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-tsu Tseng
  • Publication number: 20150255343
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20150255398
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9076847
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9059177
    Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-tsu Tseng
  • Publication number: 20150162446
    Abstract: Complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions are provided. Each CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
    Type: Application
    Filed: October 6, 2014
    Publication date: June 11, 2015
    Inventors: Xiangdong Chen, Thomas W. Dyer, Kenneth Settlemeyer, Haining S. Yang
  • Patent number: 9018097
    Abstract: A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Hanako Henry, Tze-Man Ko, Yiheng Xu, Shaoning Yao
  • Publication number: 20150054028
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 26, 2015
    Inventors: Thomas W. DYER, Haining S. YANG
  • Publication number: 20150037957
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 8896069
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W Dyer, Haining S Yang
  • Patent number: 8889504
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W Dyer, Haining S Yang