Patents by Inventor Thomas W. Williams

Thomas W. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12147907
    Abstract: A method executed by a computing device includes determining to update an entigen group within a knowledge database, where the entigen group includes a set of linked entigens that represent knowledge associated with an object. The method further includes determining a set of identigens for each word of a phrase associated with the object to produce sets of identigens. The method further includes interpreting the sets of identigens to determine a most likely meaning interpretation of the phrase and produce a new entigen group. The method further includes updating the entigen group utilizing the new entigen group to produce a curated entigen group such that a deficiency of the entigen group is resolved providing more accurate and more complete knowledge of the object.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: November 19, 2024
    Assignee: entigenlogic LLC
    Inventors: Frank John Williams, David Ralph Lazzara, Donald Joseph Wurzel, Paige Kristen Thompson, Stephen Emerson Sundberg, Ameeta Vasant Reed, Stephen Chen, Dennis Arlen Roberson, Thomas James MacTavish, Karl Olaf Knutson, Jessy Thomas, David Michael Corns, II, Andrew Chu, Theodore Mazurkiewicz, Gary W. Grube
  • Patent number: 12127074
    Abstract: In some implementations, a first computing device can send notifications at times that the first computing device is not in an expected location. A user of a second computing device can remotely configure an expected location for the first computing device, which may be a particular location for a certain period of time. During that time, the first computing device can monitor its own location and check whether it is within the expected location. If the first computing device unexpectedly leaves or fails to enter the expected location, the first computing device may transmit a notification to the second computing device. Similarly, if the first computing device loses connectivity with other devices, a server device may notify the second computing device that the location of the first computing device cannot be determined.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: October 22, 2024
    Assignee: Apple Inc.
    Inventors: Andreas E. Schobel, Swaminathan Jayaraman, Paul W. Salzman, Kevin M. Lynch, Tommy Rochette, Albert R. Howard, Siva Ganesh Movva, Thomas Chathoth Abraham, Frank De Jong, Rachel F. Needle, David John Williams, Raghunandan K. Pai, Swadesh Bhattacharya
  • Publication number: 20240338362
    Abstract: A method executed by a computing device includes determining a set of identigens for a phrase to produce sets of identigens. A set of identigens of the sets of identigens represents one or more different meanings of a word of the phrase. The method further includes interpreting, based on identigen pairing rules of a knowledge database, pairs of sequentially adjacent identigens of adjacent sets of identigens of the sets of identigens to determine a first most likely meaning interpretation of the phrase and produce a first phrase entigen group of phrase entigen groups. The method further includes identifying an inconsistency between at least two phrase entigen groups of the phrase entigen groups and obtaining an inconsistency clarification based on the inconsistency. The method further includes selecting one phrase entigen group of the phrase entigen groups based on the inconsistency clarification to produce a final phrase entigen group.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Applicant: entigenlogic LLC
    Inventors: Frank John Williams, Stephen Emerson Sundberg, Ameeta Vasant Reed, Dennis Arlen Roberson, Thomas James MacTavish, Karl Olaf Knutson, Jessy Thomas, Niklas Josiah MacTavish, David Michael Corns, II, Andrew Chu, Kyle Edward Alberth, Ali Fattahian, Zachary John McCord, Ahmad Abdelqader Abunaser, Gary W. Grube
  • Patent number: 12099536
    Abstract: A method executed by a computing device includes determining a set of identigens for each query word of a query to produce sets of identigens. A set of identigens of the sets of identigens represents one or more different meanings of a query word of the query. The method further includes determining that a first query word is associated with a first query command and determining whether to select the first query command or an identigen of a first set of identigens. When selecting the first query command, the method further includes interpreting remaining sets of identigens to produce a query entigen group that represents a most likely meaning interpretation of remaining query words. The method further includes accessing a knowledge database utilizing the query entigen group to obtain entigen information and outputting a response based on the entigen information and the first query command.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: September 24, 2024
    Assignee: entigenlogic LLC
    Inventors: Frank John Williams, Stephen Emerson Sundberg, Ameeta Vasant Reed, Dennis Arlen Roberson, Thomas James MacTavish, Karl Olaf Knutson, Jessy Thomas, Niklas Josiah MacTavish, David Michael Corns, II, Andrew Chu, Kyle Edward Alberth, Ali Fattahian, Zachary John McCord, Ahmad Abdelqader Abunaser, Gary W. Grube
  • Publication number: 20240256778
    Abstract: A method executed by a computing device includes determining a set of identigens for each query word of a query to produce sets of identigens, where a set of identigens represents different meanings of a word of the query. The method further includes interpreting the sets of identigens to produce a query entigen group. The method further includes accessing a knowledge database utilizing the query entigen group to recover a preliminary response entigen group. The method further includes modifying an answer breadth level based on a response to the preliminary response entigen group to produce an updated answer breadth level. The method further includes accessing the knowledge database utilizing the query entigen group to recover a secondary response entigen group the updated answer breadth level.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 1, 2024
    Applicant: entigenlogic LLC
    Inventors: Frank John Williams, Stephen Emerson Sundberg, Ameeta Vasant Reed, Dennis Arlen Roberson, Thomas James MacTavish, Karl Olaf Knutson, Jessy Thomas, Niklas Josiah MacTavish, David Michael Corns, II, Andrew Chu, Kyle Edward Alberth, Ali Fattahian, Zachary John McCord, Ahmad Abdelqader Abunaser, Gary W. Grube
  • Publication number: 20240249161
    Abstract: A method performed by a computing device includes generating a comparative query entigen group set based on a comparative query in accordance with identigen rules, where the comparative query entigen group set represents a most likely interpretation of the comparative query. The method further includes obtaining a first response entigen group from a knowledge database based on a first comparative query entigen group of the comparative query entigen group set. The method further includes obtaining a second response entigen group from the knowledge database based on a second comparative query entigen group of the comparative query entigen group set. The method further includes generating a comparative response based on the first response entigen group and the second response entigen group.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 25, 2024
    Applicant: entigenlogic LLC
    Inventors: Frank John Williams, David Ralph Lazzara, Stephen Emerson Sundberg, Ameeta Vasant Reed, Dennis Arlen Roberson, Thomas James MacTavish, Karl Olaf Knutson, Jessy Thomas, Niklas Josiah MacTavish, David Michael Corns, II, Andrew Chu, Theodore Mazurkiewicz, Gary W. Grube
  • Publication number: 20230132918
    Abstract: A fluid storage system includes a container defining an interior space that lacks an internal valve. A product and a propellant are stored under pressure within the interior space. A container cap includes a membrane that encloses a space defined by a coupling element, which includes a releasable fastener that releasably couples a fluid dispensing apparatus to the container. The container cap also includes a dip tube comprising a proximate end that extends at least partially into the space defined by the coupling element, and a distal end that protrudes from the space in a direction generally away from the container cap, into the interior space defined by the container. The dip tube defines an interior passage extending between the proximate end and the distal end through which the product is to be expelled from the container by the propellant.
    Type: Application
    Filed: April 30, 2021
    Publication date: May 4, 2023
    Inventors: Richard D. Hudson, James J. Johnson, Thomas W. Williams
  • Patent number: 7900105
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 1, 2011
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7836367
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7836368
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7814444
    Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: October 12, 2010
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Sanjay Ramnath, Rohit Kapur, Thomas W. Williams
  • Publication number: 20100223516
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7774663
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 10, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7743299
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 22, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7669098
    Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: February 23, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Thomas W. Williams
  • Publication number: 20100031101
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 4, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20090313514
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 24, 2009
    Publication date: December 17, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20090271673
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7596733
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 29, 2009
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20080301510
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 23, 2008
    Publication date: December 4, 2008
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams