Abstract: A method includes detecting an incomplete entigen group within a knowledge database. The incomplete entigen group includes entigens and one or more entigen relationships between at least some of the entigens. The incomplete entigen group represents knowledge of a topic. The method further includes obtaining additive content for the topic based on the incomplete entigen group and generating an additive entigen group based on the additive content. The method further includes updating the incomplete entigen group utilizing the additive entigen group to produce an updated entigen group. The method further includes indicating that the updated entigen group has an un-curated status when the additive entigen group conflicts with the incomplete entigen group.

Abstract: A fluid storage system includes a container defining an interior space that lacks an internal valve. A product and a propellant are stored under pressure within the interior space. A container cap includes a membrane that encloses a space defined by a coupling element, which includes a releasable fastener that releasably couples a fluid dispensing apparatus to the container. The container cap also includes a dip tube comprising a proximate end that extends at least partially into the space defined by the coupling element, and a distal end that protrudes from the space in a direction generally away from the container cap, into the interior space defined by the container. The dip tube defines an interior passage extending between the proximate end and the distal end through which the product is to be expelled from the container by the propellant.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.