Patents by Inventor Thomas W. Williams

Thomas W. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11096757
    Abstract: An implantable medical lead may include an electrode at a distal portion of the lead that is configured to monitor or provide therapy to a target site. The lead may include a visible indicator that is visible to the naked eye of a clinician at a medial portion of the lead that is configured to indicate when the electrodes of the lead are longitudinally and radially aligned properly to monitor or treat the target site. A clinician may insert the lead into the patient using an introducer sheath inserted to a predetermined depth into the patient and subsequently aligning the distal portion of the lead by orienting the indicator at an entry port of the introducer sheath.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 24, 2021
    Assignee: Medtronic, Inc.
    Inventors: George W. McFall, Thomas D. Brostrom, Mark T. Marshall, Dina L. Williams, Megan Harris, Keith D. Anderson, Maggie J. Pistella
  • Patent number: 7900105
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 1, 2011
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7836367
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7836368
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7814444
    Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: October 12, 2010
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Sanjay Ramnath, Rohit Kapur, Thomas W. Williams
  • Publication number: 20100223516
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7774663
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 10, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7743299
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 22, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7669098
    Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: February 23, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Thomas W. Williams
  • Publication number: 20100031101
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 4, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20090313514
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 24, 2009
    Publication date: December 17, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20090271673
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7596733
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 29, 2009
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20080301510
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 23, 2008
    Publication date: December 4, 2008
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20080294955
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 23, 2008
    Publication date: November 27, 2008
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20080256497
    Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
    Type: Application
    Filed: May 25, 2007
    Publication date: October 16, 2008
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Sanjay Ramnath, Rohit Kapur, Thomas W. Williams
  • Patent number: 7418640
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 26, 2008
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20080141188
    Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 12, 2008
    Inventors: Rohit Kapur, Thomas W. Williams
  • Patent number: 6993694
    Abstract: A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: January 31, 2006
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Thomas W. Williams, Tony Taylor, Peter Wohl, John A. Waicukauski
  • Patent number: D550290
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: September 4, 2007
    Assignee: Combustion Media, Inc.
    Inventors: Mark G. Bowring, Thomas W. Williams