Abstract: A locating structure for a bounce device in a pen, having a hollow penholder, a locating device, and a center stick. The penholder has an end with a transverse guide groove and a locating hole below the guide groove. The locating hole has a size greater than the guide groove. The locating device has a slide block with a lateral locating hole, a pushbutton with a spring locating at a bottom and received in the locating hole, a slide block inserted into the penholder through the opening. The pushbutton has a stepped end shape providing a slide tenon and a stop ring corresponding to the guide groove and the locating hole respectively, and also providing a stop flange having a size greater than the locating hole. When the pushbutton is pushed to move the slide tenon downward along the guide groove, the spring urges the stop ring to fit with the locating hole. Thus, the slide block has the writing part extend outward from the penholder.

Abstract: A rotary locator with differential position in a pen comprises an adapter head, a follower stem, and a cam. The adapter head is fixed at the top of the pen, an upper forked portion with a pivot device at the top thereof to form a groove seat, and a lower portion thereof has a central through hole. The follower stem is disposed in the central through hole and extends inward the pen. The cam is disposed in the groove seat, has two opposite flat planes on the contour thereof, an eccentric device between said two flat planes, and the eccentric device to align with the pivot device so as to rotate in the groove seat eccentrically. While the cam is turned, the follower stem displaces by way of a top thereof keeping contact with the contour of the cam. The follower stem can be located at one of two specific positions respectively because of the pivot device having different distances apart said two opposite flat planes respectively.

Abstract: An artificial neuron, which may be implemented either in hardware or software, has only one significant processing element in the form of a multiplier. Inputs are first fed through gating functions to produce gated inputs. These gated inputs are then multiplied together to produce a product which is multiplied by a weight to produce the neuron output.

Abstract: An enhanced digital beamformer (EDBF) (210, FIG. 2) is provided for use in a transceiver subsystem (200, FIG. 2) for mitigating interference and increasing the frequency reuse factor in communication systems. The EDBF is used to produce wide nulls (520, FIG. 5) in at least one steerable antenna beam pattern. By directing wide nulls at undesired signals, the EDBF provides a more efficient processing of antenna beam patterns in communication systems. The EDBF is used in geostationary satellites, non-geostationary satellites, and terrestrial communication devices. The EDBF combines a unique algorithm, a special processor, and an array antenna to significantly improve the capacity of current and future communication systems, while remaining compatible with existing modulation techniques.

Abstract: In a parallel computer system having N parallel computing units a data pipeline connects all the computing units. In addition the computing units are coupled to a random access memory so that each computing unit is assigned to one column of the memory array. To perform a digital signal processing filter operation the required coefficients are stored in the memory so that one or more different filter operations can be carried out in an interleaved way.

Abstract: An improved writing instrument includes a main casing, a head portion, a relay rod, and a tail stopper. The head portion can be connected to the main casing and is centrally provided with a tip hole for passage of a reservoir tube. The tail stopper can be fitted to the relay rod. A core tube is disposed between the main casing opposite to a rear end of the head portion and the relay rod opposite to the tail stopper. The end of the core tube facing the head portion is provided with a core chamber, whereas the end facing the tail stopper is formed with a core tube hole. The section of the core tube facing the tail stopper has a smaller external diameter, with two or more ball holes symmetrically disposed therein. A core post is inserted in the core tube and has a post ring of a larger external diameter formed at a rear end thereof to serve as a limit. An intermediate portion of the core post is provided with a core groove corresponding to the positioning balls.

Abstract: An output-processing circuit for a neural network, which may be implemented on an integrated circuit, comprises at least one latch and at least one adder. Outputs from a plurality of neurons are sequentially received by the output-processing circuit. The output-processing circuit uses gating functions to determine which neuron outputs are summed together to produce neural network outputs.

Abstract: A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.

Abstract: A method of analyzing data, particularly a speech signal, first pre-processes the signal by performing analog-to-digital conversion and cepstral analysis, producing a sequence of data frames. Then the sequence of data frames is partitioned into a plurality of data blocks. The data blocks may be subjected to further analysis, for example, by introducing them to a plurality of neural networks. The system may be implemented using either hardware or software or a combination thereof.

Abstract: A speech-recognition system for recognizing isolated words includes pre-processing circuitry for performing analog-to-digital conversion and cepstral analysis, and a plurality of neural networks which compute discriminant functions based on polynomial expansions. The system may be implemented using hardware, software, or any combination of hardware and software components. The speech wave-form of a spoken word is analyzed and converted into a sequence of data frames. The sequence of frames is partitioned into data blocks, and the data blocks are then broadcast to a plurality of neural networks. Using the data blocks, the neural networks compute polynomial expansions. The output of the neural networks is used to determine the identity of the spoken word. The neural networks utilize a training algorithm which does not require repetitive training and which yields a global minimum to each given set of training examples.

Abstract: Boundaries of spoken sounds in continuous speech are identified by classifying delimitative sounds to provide improved performance in a speech-recognition system. Delimitative sounds, those portions of continuous speech that occur between two spoken sounds, are recognized by the same method used to recognize spoken sounds. Recognition of delimitative sounds is accomplished by training a learning machine to act as a classifier which implements a discriminant function based on a polynomial expansion.

Abstract: A continuous logic system using a neural network is characterized by defining input and output variables that do not use a membership function, by employing production rules (IF/THEN rules) that relate the output variables to the input variables, and by using the neural network to compute or interpolate the outputs. The neural network first learns the given production rules and then produces the outputs in real time. The neural network is constructed of artificial neurons each having only one significant processing element in the form of a multiplier. The neural network utilizes a training algorithm which does not require repetitive training and which yields a global minimum to each given set of input vectors.

Abstract: A method of operating a neural network and a neural network, which is implemented either in hardware or software, is constructed of neurons or neuron circuits each having only one significant processing element in the form of a multiplier. The neural network utilizes a training algorithm which does not require repetitive training and which yields a global minimum to each given set of input vectors.

Abstract: A neural network, which may be implemented either in hardware or software, is constructed of neurons or neuron circuits each having only one significant processing element in the form of an adder. Each neural network further includes circuits for applying a logarithmic function to its inputs and for applying an inverse-logarithmic function to the outputs of its neurons. The neural network utilizes a training algorithm which does not require repetitive training and which yields a global minimum to each given set of input vectors.

Abstract: A computer processor that performs operations in a logarithmic number system (LNS) domain includes a log converter (20) which generates log signals, a data pipeline (22), a plurality of processing elements (231a-f) coupled to respective stages (24a-d) of the data pipeline, an inverse-log converter (28), and a programmable accumulator (232) that performs various summing operations to produce an output signal. An instruction, selected from a set of instructions, is decoded by a control unit (234) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters.

Abstract: A computer processor that performs operations in a logarithmic number system (LNS) domain includes an input log converter (20), a feedback log converter (303), a first data pipeline (304), a second data pipeline (306), a plurality of processing elements (26a-f) coupled to respective stages of the data pipelines, an inverse-log converter (28), and a programmable accumulator (232) which produces output signals. An instruction, selected from a set of instructions, is decoded by a control unit (235) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters.

Abstract: A handwriting recognition system achieves a higher recognition rate by using a feature extraction method which computes features based on multiple data frames. A plurality of data frames is generated from handwritten text received by the system. Each data frame includes samples taken from the handwritten text. Individual-frame features are extracted from individual data frames, and in turn, multi-frame features are extracted from individual-frame features which correspond to different data frames.

Abstract: A communications device (20) that is responsive to voice commands is provided. The communications device (20) can be a two-way radio, cellular telephone, PDA, or pager. The communications device (20) includes an interface (22) for allowing a user to access a communications channel according a control signal and a speech-recognition system (24) for producing the control signal in response to a voice command. Included in the speech recognition system (24) are a feature extractor (26) and one or more classifiers (28) utilizing polynomial discriminant functions.

Abstract: A computing device, which may be implemented as an integrated circuit, is constructed of a microprocessor and one or more neural network co-processors. The microprocessor normally executes programs which transfer data to the neural network co-processors, which are used to compute complicated mathematical functions. Direct Memory Access (DMA) is also used to transfer data.Each neural network co-processor interfaces to the microprocessor in a manner substantially similar to that of a conventional memory device. The co-processor does not require any instructions and is configured to execute mathematical operations simply by being pre-loaded with gating functions and weight values. In addition, the co-processor executes a plurality of arithmetic operations in parallel, and the results of such operations are simply read from the co-processor.