Abstract: An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.

Abstract: A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.

Abstract: Transistor gate linewidths can be made to be effectively smaller by etching a notch at the bottom of the gate to reduce the effective linewidth. This can be done by etching at a layer interface, such as a silicon-germanium interface in an over-etch step.

Abstract: A substrate processing method comprises providing a substrate 105 comprising etch resistant material 210 in a process zone 155, such as an energized gas zone in a process chamber 110. The etch resistant material 210 may comprise a resist material 230 over mask material 240. The process may further comprise removing the etch resistant material 210, such as the resist material 230, in the process zone 155 before etching underlying layers.

Abstract: A process for etching multiple layers on a substrate 25 in an etching chamber 30 and cleaning a multilayer etchant residue formed on the surfaces of the walls 45 and components of the etching chamber 30. In multiple etching steps, process gas comprising different compositions of etchant gas is used to etch layers on the substrate 25 thereby depositing a compositionally variant etchant residue inside the chamber 30. In one cleaning step, a first cleaning gas is added to the process gas to clean a first residue or to suppress deposition of the first residue onto the chamber surfaces. In a second cleaning step, another residue composition is cleaned off the chamber surfaces using a second cleaning gas composition.

Abstract: A substrate processing apparatus comprises a chamber 28 capable of processing a substrate 20. A radiation source 58 provides radiation that is at least partially reflected from the substrate in the chamber. A radiation detector 62 is provided to detect the reflected radiation and generate a signal. A controller 100 is adapted to receive the signal and determine a property of the substrate 20 in situ during processing, before an onset of during or after processing of a material on the substrate 20.

Abstract: The present invention provides a process of etching polysilicon gates using a silicon dioxide hard mask. The process includes exposing a substrate with a polysilicon layer formed thereon to a plasma of a process gas, which includes a base gas and an additive gas. The base gas includes HBr, Cl2, O2, and the additive gas is NF3 and/or N2. By changing a volumetric flow ratio of the additive gas to the base gas, the etch rate selectivity of polysilicon to silicon dioxide may be increased, which allows for a thinner hard mask, better protection of the gate oxide layer, and better endpoint definition and control. Additionally, when the polysilicon layer includes both N-doped and P-doped regions, the additive gas includes both NF3 and N2, and by changing a volumetric flow ratio of NF3 to N2, the etching process may be tailored to provide optimal results in N/P loading and microloading.

Abstract: An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.

Abstract: A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.

Abstract: One embodiment of the present invention is an etching method for use in fabricating an integrated circuit device on a wafer or substrate in an inductively coupled plasma reactor in a passivation-driven etch chemistry, which method includes steps of: (a) providing a passivation-driven etch chemistry precursor in a chamber of the reactor wherein a first coil is disposed to supply energy primarily to an outer portion of the chamber and a second coil is disposed to supply energy primarily to an inner portion of the chamber; and (b) providing power to the first coil and the second coil in a ratio of power supplied to the first coil and power supplied to the second coil greater than 1.

Abstract: One embodiment of the present invention is a method used to fabricate an integrated circuit device on a wafer or substrate at a stage where a gate oxide is disposed over the wafer or substrate, a polysilicon layer is disposed thereover, a patterned hardmask is disposed thereover, a patterned antireflective coating is disposed thereover, and a patterned photoresist is disposed thereover, the method including steps of: (a) before stripping the photoresist, etching the polysilicon utilizing a first etch chemistry for a first period of time; and (b) etching the polysilicon utilizing a second etch chemistry for a second period of time.

Abstract: A process of reducing critical dimension (CD) microloading in dense and isolated regions of etched features of silicon-containing material on a substrate uses a plasma of an etchant gas and an additive gas. In one version, the etchant gas comprises halogen species absent fluorine, and the additive gas comprises fluorine species and carbon species, or hydrogen species and carbon species.

Abstract: Transistor gate linewidths can be made to be effectively smaller by etching a notch at the bottom of the gate to reduce the effective linewidth. This can be done by etching at a layer interface, such as a silicon-germanium interface. in an over-etch step.

Abstract: A chamber 28 comprises a radiation source 58 capable of emitting radiation having a wavelength that is substantially absorbed in a predetermined pathlength in a thickness of a layer 22 on a substrate, and a radiation detector 62 adapted to detect the radiation. The radiation is substantially absorbed in a first thickness of the layer 22, and after at least partial processing of the layer 22, is at least partially transmitted through a second thickness of the layer 22 and reflected by one or more underlayers 24 of the substrate 20.

Abstract: A focused ion beam having a cross section of submicron diameter, a high ion current, and a narrow energy range is generated from a target comprised of particle source material by laser ablation. The method involves directing a laser beam having a cross section of critical diameter onto the target, producing a cloud of laser ablated particles having unique characteristics, and extracting and focusing a charged particle beam from the laser ablated cloud. The method is especially suited for producing focused ion beams for semiconductor device analysis and modification.

Abstract: A substrate 20 in a process chamber 42 is processed at process conditions suitable for processing a layer 30 on the substrate 20, the process conditions comprising one or more of process gas composition and flow rates, power levels of process gas energizers, process gas pressure, and substrate temperature. The intensity of a reflected light beam 78 reflected from the layer 30 on the substrate 20 is measured over time, to determine a measured waveform pattern. The measured waveform pattern is compared to a pretetermined characteristic waveform pattern, and when the two waveform patterns are similar or substantially the same, the process conditions are changed to change a rate of processing or a process selectivity ratio of the layer 30 on the substrate 20 before the entire layer 30 is completely processed.