Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their suicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective layer.

Abstract: By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

Abstract: By maintaining the gate electrode covered during the process flow for forming metal silicide regions in the drain and source of a field effect transistor, an appropriate metal silicide may be formed on the gate electrode which meets the requirement for aggressive gate length scaling. Preferably, a nickel silicide is formed on the gate electrode, whereas the drain and source regions receive the well-established cobalt disilicide. Additionally, the gate electrode dopant profile is effectively decoupled from the drain and source dopant profile.

Abstract: By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

Abstract: The present invention provides a technique that enables the formation of a recessed spacer element by using an anisotropically deposited etch stop layer. Accordingly, in subsequent cleaning processes, material residues of the etch stop layer may be efficiently removed from upper sidewall portions of a line element, thereby increasing the available area for a diffusion path in a subsequent silicidation process. The anisotropic deposition of the etch stop layer may be accomplished by high density plasma enhanced CVD or by directional sputter techniques.

Abstract: By performing a sequence of selective epitaxial growth processes with at least two different species, or by introducing a first dopant species prior to the epitaxial growth of a drain and source region, a halo region may be formed in a highly efficient manner, while at the same time the degree of lattice damage in the epitaxially grown semiconductor region is maintained at a low level.

Abstract: The present invention describes a method for forming different types of gate insulation layers, wherein the formation of one type of gate insulation layer is highly decoupled from the formation of the other type of gate insulation layer. Thus, in some embodiments, critical oxidation processes may finely be tuned on an individual basis. This is accomplished by providing a mask layer that may substantially prevent any impact on an initially made insulation layer during a subsequent manufacturing process of a second gate insulation layer.

Abstract: The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

Abstract: By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.

Abstract: In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.

Abstract: A dislocation region is formed by implanting a light inert species, such as hydrogen, to a specified depth and with a high concentration, and by heat treating the inert species to create “nano” bubbles, which enable a certain mechanical decoupling to underlying device regions, thereby allowing a more efficient creation of strain that is induced by an external stress-generating source. In this way, strain may be created in a channel region of a field effect transistor by, for instance, a stress layer or sidewall spacers formed in the vicinity of the channel region.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: The present invention allows the formation of sidewall spacers adjacent a feature on a substrate without there being an undesirable erosion of the feature. The feature is covered by one or more protective layers. A layer of a spacer material is deposited over the feature and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers are substantially not affected by the etchant. Thus, the one or more protective layers protect the feature from being exposed to the etchant.

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: The present invention makes it possible to precisely deposit a material adjacent a feature on a substrate. A layer of the material is deposited on the substrate. The layer is planarized and exposed to an etchant. The etchant is adapted to selectively remove the material. The exposing of the layer to the etchant is stopped prior to a complete removal of the layer.

Abstract: The present invention provides a technique that enables the formation of a recessed spacer element by using an anisotropically deposited etch stop layer. Accordingly, in subsequent cleaning processes, material residues of the etch stop layer may be efficiently removed from upper sidewall portions of a line element, thereby increasing the available area for a diffusion path in a subsequent silicidation process. The anisotropic deposition of the etch stop layer may be accomplished by high density plasma enhanced CVD or by directional sputter techniques.

Abstract: By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.