Patents by Inventor Thorsten Meyer

Thorsten Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203238
    Abstract: A method for manufacturing a semiconductor panel is disclosed. In one example, the method includes providing a first preformed polymer form. The method further includes arranging multiple semiconductor chips over the first preformed polymer form. The method further includes attaching a second preformed polymer form to the first preformed polymer form, wherein the semiconductor chips are arranged between the attached preformed polymer forms, and wherein the attached preformed polymer forms form the semiconductor panel encapsulating the semiconductor chips.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 25, 2020
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Andreas Grassmann
  • Publication number: 20200203310
    Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Thorsten Meyer, Gerald Ofner, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss, Peter Scherl
  • Patent number: 10629575
    Abstract: A semiconductor chip assembly includes first and second semiconductor dies that each include opposite facing upper and lower sides and an outer edge side, and an electrical interposer having opposite facing first and second conductive surfaces and a conductive connection between the conductive surfaces. The second semiconductor die is mounted on top of the first semiconductor die and the interposer such that the lower side of the second semiconductor die faces the first semiconductor die and the interposer, a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die, and a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die. The first conductive surface is electrically connected to a first terminal that is disposed on a lower side of the second semiconductor die.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Techologies AG
    Inventors: Thorsten Scharf, Carsten Ahrens, Helmut Brech, Martin Gruber, Thorsten Meyer, Matthias Zigldrum
  • Patent number: 10625769
    Abstract: A motor vehicle steering system is disclosed. The system includes a steering spindle consisting of spindle members which are non-rotatably connected to one another. One end of a spindle member has a spline shaft profile and is introduced into a sleeve-like intermediate piece which is arranged on the other spindle member and, on the inner periphery, has a negative-shaped spline shaft profile with respect to the spline shaft profile such that the spindle member is plug-connected to the intermediate piece. In order for the spindle members to be able to be connected to each other with minimal effort even in the event of visual inaccessibility, a circumferential guide contour pointing toward the intermediate piece is formed on the spindle member. The guide contour is upstream of the spline shaft profile toward the intermediate piece and is perforated by grooves of the spline shaft profile to form convex guide segments.
    Type: Grant
    Filed: February 7, 2015
    Date of Patent: April 21, 2020
    Assignee: Daimler AG
    Inventors: Axel Hebenstreit, Hans-Dieter Loeffler, Thorsten Meyer, Marco Schwieger
  • Publication number: 20200085779
    Abstract: The present invention provides compounds for use in the treatment of respiratory diseases of animals, especially Bovine or Swine Respiratory disease (BRD and SRD).
    Type: Application
    Filed: December 22, 2017
    Publication date: March 19, 2020
    Applicant: Intervet Inc.
    Inventors: Thorsten Meyer, Ralf Warrass, Joachim Ullrich, Michael Berger, Michael Linder
  • Patent number: 10566309
    Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gerald Ofner, Peter Scherl, Stephan Bradl, Stefan Miethaner, Alexander Heinrich, Horst Theuss
  • Publication number: 20200021002
    Abstract: A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Maciej Wojnowski, Dirk Hammerschmidt, Walter Hartner, Johannes Lodermeyer, Chiara Mariotti, Thorsten Meyer
  • Patent number: 10535634
    Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Vijay K. Nair, Chuan Hu, Thorsten Meyer
  • Patent number: 10522454
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Andreas Wolter, Georg Seidemann, Sven Albers, Christian Geissler
  • Publication number: 20190363052
    Abstract: Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.
    Type: Application
    Filed: January 28, 2016
    Publication date: November 28, 2019
    Applicant: Intel IP Corporation
    Inventors: Sanka Ganesan, Thorsten Meyer, Gerald Ofner
  • Publication number: 20190352256
    Abstract: The present invention discloses compounds of formula (I) that are useful in the treatment of respiratory diseases of animals, especially Bovine or Swine Respiratory disease (BRD and SRD).
    Type: Application
    Filed: December 22, 2017
    Publication date: November 21, 2019
    Applicant: Intervet Inc.
    Inventors: Michael Berger, Thorsten Meyer, Joachim Ullrich, Ralf Warrass
  • Patent number: 10453804
    Abstract: A package is described for a radio frequency die that has a backside conductive plate. One example includes a conductive plate, a semiconductor die having a front side and a back side, the back side being attached to the plate, a radio frequency component attached to the plate, a dielectric filled cavity in the plate adjacent to the radio frequency component, and a redistribution layer attached to the front side of the die for external connection.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Thorsten Meyer
  • Publication number: 20190304858
    Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Scharf, Ralf Otremba, Thomas Bemmerl, Irmgard Escher-Poeppel, Martin Gruber, Michael Juerss, Thorsten Meyer, Xaver Schloegel
  • Patent number: 10394280
    Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 27, 2019
    Assignee: INTEL CORPORATION
    Inventors: Thorsten Meyer, Dirk Plenkers, Hans-Joachim Barth, Bernd Waidhas, Yen Hsiang Chew, Kooi Chi Ooi, Howe Yin Loo
  • Publication number: 20190259688
    Abstract: A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 22, 2019
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Scharf, Thorsten Meyer
  • Patent number: 10373844
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 6, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Publication number: 20190221349
    Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Inventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
  • Publication number: 20190221531
    Abstract: A semiconductor device includes a semiconductor die having an active main surface and an opposite main surface opposite the active main surface. The semiconductor device further includes an antenna arranged on the active main surface of the semiconductor die and a recess arranged on the opposite main surface of the semiconductor die. The recess is arranged over the antenna.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Thorsten Meyer, Walter Hartner, Maciej Wojnowski
  • Patent number: 10354925
    Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface, first trenches and second trenches extending from the first surface into the semiconductor body, at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches, and at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches. The first trenches extend from the first surface into the semiconductor body deeper than a channel zone of the lateral IGFET and confine the channel zone.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Werner Schwetlick
  • Publication number: 20190206833
    Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.
    Type: Application
    Filed: December 23, 2015
    Publication date: July 4, 2019
    Inventors: Thorsten MEYER, Klaus REINGRUBER, Georg SEIDEMANN, Andreas WOLTER, Christian GEISSLER, Sven ALBERS