Patents by Inventor Thorsten Schedel

Thorsten Schedel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11537039
    Abstract: A photomask mask assembly includes a reflective photomask and a protection structure. The reflective photomask includes a substrate and a reflective multilayer on a first substrate surface of the substrate at a front side of the reflective photomask. The protection structure is on a second substrate surface of the substrate at a backside of the reflective photomask, and is detachable from the reflective photomask at a temperature below 150 degree Celsius.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 27, 2022
    Assignee: ADVANCED MASK TECHNOLOGY CENTER GMBH & CO. KG
    Inventors: Thorsten Schedel, Markus Bender, Andreas Schenke
  • Publication number: 20200225571
    Abstract: A photomask mask assembly includes a reflective photomask and a protection structure. The reflective photomask includes a substrate and a reflective multilayer on a first substrate surface of the substrate at a front side of the reflective photomask. The protection structure is on a second substrate surface of the substrate at a backside of the reflective photomask, and is detachable from the reflective photomask at a temperature below 150 degree Celsius.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Inventors: Thorsten Schedel, Markus Bender, Andreas Schenke
  • Patent number: 10031409
    Abstract: A reflective photomask includes a substrate with a substrate layer of a low thermal expansion material. The substrate layer includes a main portion of a first structural configuration and an auxiliary portion of a second structural configuration of the low thermal expansion material. The auxiliary portion is formed in a frame section surrounding a pattern section of the substrate. A multilayer mirror is formed on a first surface of the substrate. A reflectivity of the multilayer mirror is at least 50% at an exposure wavelength below 15 nm. A frame trench extending through the multilayer mirror exposes the substrate in the frame section. The auxiliary portion may include scatter centers for out-of-band radiation.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 24, 2018
    Assignee: ADVANCED MASK TECHNOLOGY CENTER GmbH & CO. KG
    Inventors: Markus Bender, Thorsten Schedel
  • Publication number: 20170108766
    Abstract: A reflective photomask includes a substrate with a substrate layer of a low thermal expansion material. The substrate layer includes a main portion of a first structural configuration and an auxiliary portion of a second structural configuration of the low thermal expansion material. The auxiliary portion is formed in a frame section surrounding a pattern section of the substrate. A multilayer mirror is formed on a first surface of the substrate. A reflectivity of the multilayer mirror is at least 50% at an exposure wavelength below 15 nm. A frame trench extending through the multilayer mirror exposes the substrate in the frame section. The auxiliary portion may include scatter centres for out-of-band radiation.
    Type: Application
    Filed: June 10, 2016
    Publication date: April 20, 2017
    Applicant: Advanced Mask Technology Center GmbH & Co. KG
    Inventors: Markus Bender, Thorsten Schedel
  • Patent number: 8097955
    Abstract: Interconnect structures and methods are disclosed. In one embodiment, an interconnect structure includes a via extendable through a workpiece from a first side of the workpiece to a second side of the workpiece. The via is partially filled with a conductive material and has sidewalls. The interconnect structure includes a contact coupled to the conductive material in the via proximate the first side of the workpiece. The conductive material in the via comprises a recessed region comprising a landing zone proximate the second side of the workpiece.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: January 17, 2012
    Assignee: Qimonda AG
    Inventors: Bernd Zimmermann, Volker Berghof, Stefan Ruckmich, Thorsten Schedel
  • Publication number: 20100090317
    Abstract: Interconnect structures and methods are disclosed. In one embodiment, an interconnect structure includes a via extendable through a workpiece from a first side of the workpiece to a second side of the workpiece. The via is partially filled with a conductive material and has sidewalls. The interconnect structure includes a contact coupled to the conductive material in the via proximate the first side of the workpiece. The conductive material in the via comprises a recessed region comprising a landing zone proximate the second side of the workpiece.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Inventors: Bernd Zimmermann, Volker Berghof, Stefan Ruckmich, Thorsten Schedel
  • Publication number: 20090166848
    Abstract: In a method for making a semiconductor component, an integrated circuit is provided with a chip pad on an active side. A conductive track is connected to the chip pad and a passivation layer covers the conductive track. Forming the conductive track includes structuring an uneven sidewall for form closure with the passivation layer.
    Type: Application
    Filed: December 29, 2007
    Publication date: July 2, 2009
    Inventors: Volker Berghof, Thorsten Schedel
  • Patent number: 7304716
    Abstract: By a unit for determining fractions of a substance in a gas or gas mixture, measurements are carried out on the gas or gas mixture for purging a lens in a projection apparatus for projecting patterns onto a substrate. The results of a first measurement on the gas fed to the lens are compared with the results of a measurement of the gas removed from the lens. If, the substance is a contaminating substance that leads to a deposit on the lens under the influence of high-energy radiation from an illumination source, the difference is used to infer photochemical reactions on the surface of the lens that lead disadvantageously to the deposition. A signal is generated as a consequence of the comparison and is used to take preventive measures against a degradation of the lens. Mass spectrometers, electric or optical sensors and other known methods for substance analysis are used as measurement units.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: December 4, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Schedel, Sebastian Schmidt, Günter Hraschan
  • Patent number: 7248365
    Abstract: The unevennesses of a chuck are measured at various positions and are stored, as discrepancies from an idealized plane, in a databank. The measured discrepancies are used to calculate corrections for the predetermined settings for the focus distance and/or the tilt of the chuck. These corrections are in each case used differently for adjusting the respective exposure of the exposure areas.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: July 24, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Schedel, Martin Rössiger
  • Patent number: 7186484
    Abstract: A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two masks (3, 4), comprising two structure elements (10, 20) formed on a respective one of the masks (1, 2). The structure elements (10, 20) overlap with regard to their position on the masks so that, during the projection of the second structure element (20), an electrically conductive structure (30) formed on the basis of the first structure element on the wafer (5) is overformed by removal of a portion (31). In an electrical line width measurement, the reduced width (CD, CD30a) of the structure (30) is measured and compared either with the original width (62) or with that width (CD30b) of a further partial element (30b) produced by the overforming.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventors: Heiko Hommen, Jens Stäcker, Maria de la Piedad Fernandez-Martinez, Jens Uwe Bruch, Thorsten Schedel
  • Publication number: 20070005170
    Abstract: A method is provided for the preferred processing of a workpiece of highest priority in a plant with a number of processing steps and at least one processing station for each processing step. A workpiece of highest priority to be added is inserted at the head of the line before the first processing step and is passed to the next processing station of this processing step that becomes free. For each subsequent processing step, a processing station of this processing step is kept free or preallocated. In the event that there are a number of processing stations for a processing step, the one which experiences the shortest standstill time on account of being kept free or at which the workpiece of highest priority experiences the shortest waiting time on account of it being preallocated being selected from among these processing stations. The workpiece of highest priority is passed on to the processing station kept free or preallocated and is once again inserted at the head of the line.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventor: Thorsten Schedel
  • Patent number: 6979522
    Abstract: A batch of semiconductor wafers are exposed after an alignment in a wafer stepper or scanner and each of their alignment parameters are determined. Using, e.g., a linear formula with tool specific coefficients, the overlay accuracy can be calculated from these alignment parameters in advance with a high degree of accuracy as if a measurement with an overlay inspection tool had been performed. The exposure tool-offset can be adjusted on a wafer-to-wafer basis to correct for the derived overlay inaccuracy. Moreover, the alignment parameters for a specific wafer can be used to change the tool-offset for the same wafer prior to exposure. The required inspection tool capacity is advantageously reduced, the wafer rework decreases, and time is saved to perform the exposure step.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: December 27, 2005
    Assignee: Infineon Technologies AG
    Inventors: Heiko Hommen, Ralf Otto, Thorsten Schedel, Sebastian Schmidt, Thomas Fischer
  • Publication number: 20050269748
    Abstract: By a unit for determining fractions of a substance in a gas or gas mixture, measurements are carried out on the gas or gas mixture for purging a lens in a projection apparatus for projecting patterns onto a substrate. The results of a first measurement on the gas fed to the lens are compared with the results of a measurement of the gas removed from the lens. If, the substance is a contaminating substance that leads to a deposit on the lens under the influence of high-energy radiation from an illumination source, the difference is used to infer photochemical reactions on the surface of the lens that lead disadvantageously to the deposition. A signal is generated as a consequence of the comparison and is used to take preventive measures against a degradation of the lens. Mass spectrometers, electric or optical sensors and other known methods for substance analysis are used as measurement units.
    Type: Application
    Filed: May 12, 2005
    Publication date: December 8, 2005
    Inventors: Thorsten Schedel, Sebastian Schmidt, Gunter Hraschan
  • Publication number: 20050260510
    Abstract: A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two masks (3, 4), comprising two structure elements (10, 20) formed on a respective one of the masks (1, 2). The structure elements (10, 20) overlap with regard to their position on the masks so that, during the projection of the second structure element (20), an electrically conductive structure (30) formed on the basis of the first structure element on the wafer (5) is overformed by removal of a portion (31). In an electrical line width measurement, the reduced width (CD, CD30a) of the structure (30) is measured and compared either with the original width (62) or with that width (CD30b) of a further partial element (30b) produced by the overforming.
    Type: Application
    Filed: September 24, 2004
    Publication date: November 24, 2005
    Inventors: Heiko Hommen, Jens Stacker, Maria de la Piedad Fernandez-Martinez, Jens Bruch, Thorsten Schedel
  • Patent number: 6908775
    Abstract: In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of alignment structures in an exposure field of a corresponding predefined set of exposure fields can be handled by selecting an alignment structure in a substitute exposure field. The latter exposure field need not be part of the predefined set of exposure fields, that is, an inter-field change may be effected. The number of alignment measurements on a wafer remains constant and the quality is increased. Alternatively, when using another alignment structure in the same exposure field—by effecting an intra-field change—the method becomes particularly advantageous when different minimum structure sizes are considered for the substitute targets. Due to the different selectivity in, say, a previous CMP process, such targets might not erode and do not cause an error in a measurement, thus providing an increased alignment or overlay quality.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: June 21, 2005
    Assignee: Infineon Technologies AG
    Inventors: Rolf Heine, Sebastian Schmidt, Thorsten Schedel
  • Publication number: 20050106476
    Abstract: An item of information about the respective positions (501, 502, 601, 602) of at least two structure elements (50, 60) on a mask is provided. The displacement of the positional positions during the imaging by the lens system of the exposure apparatus, the displacement being governed by lens aberration, is measured and correction values (540, 640) are determined for each of the structure elements. Using the correction values (540, 640) the positions (501, 502, 601, 602) are changed in order to form new positions (505, 506, 605, 606) of the structure elements (50, 60) in such a way that the aberration effects can be compensated for. A mask (40) adapted to the exposure apparatus is exposed with the structures at the changed positions. The variation in the positional accuracies and the structure width distributions which is governed by the aberration of lenses is advantageously reduced.
    Type: Application
    Filed: October 14, 2004
    Publication date: May 19, 2005
    Inventors: Jens Hassmann, Johannes Kowalewski, Gerhard Kunkel, Thorsten Schedel, Uwe Schroder, Ina Voigt
  • Patent number: 6892108
    Abstract: Processing parameters of at least one plate-shaped object, e.g. a semiconductor device or wafer, or a flat panel display, in a processing tool are adjusted depending on which processing device out of at least one set of processing devices has been used for the semiconductor device in a preceding step. A virtual or physical tag is generated, which connects the semiconductor device identification with the processing device identification. This enables a compensation of tool-dependent effects in previous processing of a single device. An example is chemical mechanical polishing prior to lithography, where alignment marks can be deteriorated differently between CMP-units. The amount of compensation is detected and evaluated by metrology tools, which—depending on the sequence of the metrology step relative to the processing step to be adjusted—either feed-forward or feed-backward their results to the processing tool. The yield of semiconductor device production is advantageously increased.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: May 10, 2005
    Assignees: Infineon Technologies SC300 GmbH & Co. KG, Infineon Technologies AG, Motorola Inc.
    Inventors: Karl Mautz, Sebastian Schmidt, Thorsten Schedel
  • Patent number: 6887722
    Abstract: A method for exposing a semiconductor wafer compensates for the effects of process inhomogeneities, e.g. in semiconductor etching or deposition processes, by individually adjusting sets of exposure parameters of an exposure tool for any exposure field. The exposure parameters are preferably the dose and the focus, which are varied across the semiconductor wafer.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 3, 2005
    Assignee: Infineon Technologies SC300 GmbH & Co. KG
    Inventors: Thorsten Schedel, Torsten Seidel
  • Patent number: 6861331
    Abstract: Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the locational position of alignment marks and/or oblique measurement structures. Measurement structures are formed preferably in the frame region of product wafers comprising electrical circuits to be formed and their locational positions before and after the effect of the process that has an effect are compared individually for purpose of determining the positional displacement for each relevant exposure field. From this there is determined either directly a “shot”-fine correction value for the individual exposure or at least one nonlinear function for the correction in dependence on the position of the measurement structures on the wafer. The corrections are applied to the exposure fields after alignment to the alignment marks overformed by the process in dependence on their position on the wafer.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: March 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Martin Rössiger, Thorsten Schedel, Jens Stäcker
  • Patent number: 6806008
    Abstract: A test reticle having a pad and antenna structures with varying critical dimensions is provided to measure sidewall angles developing in the resist sidewalls of clear lines. These sidewall angles originate from resist flow due to the occurrence of excessively high temperatures in a resist process on a lithographic track after the exposure of a semiconductor wafer. A scanning electron microscope is used to perform the measurement. A sequence of temperatures is applied in each postbake step to process a wafer, and the sidewall angle is determined afterwards from e.g. a critical dimension measurement with a known resist thickness. An error signal is issued, if a threshold value of a sidewall angle is exceeded. The temperature of the resist process, e.g. the postbake, is then adjusted to a temperature below the temperature causing the warning signal.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: October 19, 2004
    Assignee: Infineon Technologies SC300 GmbH & Co. KG
    Inventors: Thorsten Schedel, Torsten Seidel