Abstract: After exposing a semiconductor wafer, quality parameters, for example, the critical dimension, the overlay accuracy, and alignment parameters, etc. are measured in successive inspections and are compared with tolerance range widths that are specified dynamically by calculating the range from measured values of one or more of the other quality parameters. For example, the tolerance range width for the overlay accuracy can be increased for smaller measured critical dimension values of the same structures without affecting the functionality of the integrated circuit. Using a forward mechanism, the tolerance ranges can also be adjusted with the quality parameter measurements from a first layer to the quality parameter tolerance range width of a second layer.

Abstract: Processing parameters of at least one plate-shaped object, e.g. a semiconductor device or wafer, or a flat panel display, in a processing tool are adjusted depending on which processing device out of at least one set of processing devices has been used for the semiconductor device in a preceding step. A virtual or physical tag is generated, which connects the semiconductor device identification with the processing device identification. This enables a compensation of tool-dependent effects in previous processing of a single device. An example is chemical mechanical polishing prior to lithography, where alignment marks can be deteriorated differently between CMP-units. The amount of compensation is detected and evaluated by metrology tools, which—depending on the sequence of the metrology step relative to the processing step to be adjusted—either feed-forward or feed-backward their results to the processing tool. The yield of semiconductor device production is advantageously increased.

Abstract: A processing tool for manufacturing semiconductor devices, e.g. a lithography cluster, has a device transfer area with an optical sensor (e.g. CCD-camera), and an illumination system. A substrate (e.g., a semiconductor wafer, a reticle, or a mask for exposure on the wafer) that is transferred to or from one of its processing chambers can be scanned during its movement at low resolution. Scanning is performed before and after processing in at least one the processing chambers of the processing tool. The images are compared and optionally subtracted from each other. Defects imposed to the substrate due to contaminating particles only during the present processes with sizes larger than 10 &mgr;m are visible on the subtracted image. Defects imposed earlier are diminished as well as structures formed from a mask pattern below 10 &mgr;m. Pattern recognition allows efficient classification of the defects just detected in a processing tool.

Abstract: The unevennesses of a chuck are measured at various positions and are stored, as discrepancies from an idealized plane, in a databank. The measured discrepancies are used to calculate corrections for the predetermined settings for the focus distance and/or the tilt of the chuck. These corrections are in each case used differently for adjusting the respective exposure of the exposure areas.

Abstract: In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of alignment structures in an exposure field of a corresponding predefined set of exposure fields can be handled by selecting an alignment structure in a substitute exposure field. The latter exposure field need not be part of the predefined set of exposure fields, that is, an inter-field change may be effected. The number of alignment measurements on a wafer remains constant and the quality is increased. Alternatively, when using another alignment structure in the same exposure field—by effecting an intra-field change—the method becomes particularly advantageous when different minimum structure sizes are considered for the substitute targets. Due to the different selectivity in, say, a previous CMP process, such targets might not erode and do not cause an error in a measurement, thus providing an increased alignment or overlay quality.

Abstract: Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the locational position of alignment marks and/or oblique measurement structures. Measurement structures are formed preferably in the frame region of product wafers comprising electrical circuits to be formed and their locational positions before and after the effect of the process that has an effect are compared individually for purpose of determining the positional displacement for each relevant exposure field. From this there is determined either directly a “shot”-fine correction value for the individual exposure or at least one nonlinear function for the correction in dependence on the position of the measurement structures on the wafer. The corrections are applied to the exposure fields after alignment to the alignment marks overformed by the process in dependence on their position on the wafer.

Abstract: A method for exposing a semiconductor wafer compensates for the effects of process inhomogeneities, e.g. in semiconductor etching or deposition processes, by individually adjusting sets of exposure parameters of an exposure tool for any exposure field. The exposure parameters are preferably the dose and the focus, which are varied across the semiconductor wafer.

Abstract: A batch of semiconductor wafers are exposed after an alignment in a wafer stepper or scanner and each of their alignment parameters are determined. Using, e.g., a linear formula with tool specific coefficients, the overlay accuracy can be calculated from these alignment parameters in advance with a high degree of accuracy as if a measurement with an overlay inspection tool had been performed. The exposure tool-offset can be adjusted on a wafer-to-wafer basis to correct for the derived overlay inaccuracy. Moreover, the alignment parameters for a specific wafer can be used to change the tool-offset for the same wafer prior to exposure. The required inspection tool capacity is advantageously reduced, the wafer rework decreases, and time is saved to perform the exposure step.

Abstract: While a first leading semiconductor wafer (11) already processed in a process appliance (1) and belonging to a batch is being measured in a microscope measuring instrument (2) in relation to values for the structure parameters 30, a second or further semiconductor wafer (12) belonging to the batch is processed in the process appliance (1). An event signal (100) reports, for example, an inspection carried out successfully of the first wafer, so that the following wafers (12) no longer need to be inspected. Using the measured results, the process parameters (31) of the process appliance (1) are automatically readjusted. Events such as maintenance work or parameter drifts in trend maps etc. are detected in control units (8 or 9) and, via the output of an event signal (102), for example in an event database (40), lead to the event-based selection of structure parameters (30′) to be measured and/or to the initiation of a leading wafer (11).

Abstract: There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.

Abstract: After exposing a semiconductor wafer, quality parameters, for example, the critical dimension, the overlay accuracy, and alignment parameters, etc. are measured in successive inspections and are compared with tolerance range widths that are specified dynamically by calculating the range from measured values of one or more of the other quality parameters. For example, the tolerance range width for the overlay accuracy can be increased for smaller measured critical dimension values of the same structures without affecting the functionality of the integrated circuit. Using a forward mechanism, the tolerance ranges can also be adjusted with the quality parameter measurements from a first layer to the quality parameter tolerance range width of a second layer.

Abstract: A test reticle having a pad and antenna structures with varying critical dimensions is provided to measure sidewall angles developing in the resist sidewalls of clear lines. These sidewall angles originate from resist flow due to the occurrence of excessively high temperatures in a resist process on a lithographic track after the exposure of a semiconductor wafer. A scanning electron microscope is used to perform the measurement. A sequence of temperatures is applied in each postbake step to process a wafer, and the sidewall angle is determined afterwards from e.g. a critical dimension measurement with a known resist thickness. An error signal is issued, if a threshold value of a sidewall angle is exceeded. The temperature of the resist process, e.g. the postbake, is then adjusted to a temperature below the temperature causing the warning signal.

Abstract: While a first leading semiconductor wafer (11) already processed in a process appliance (1) and belonging to a batch is being measured in a microscope measuring instrument (2) in relation to values for the structure parameters 30, a second or further semiconductor wafer (12) belonging to the batch is processed in the process appliance (1). An event signal (100) reports, for example, an inspection carried out successfully of the first wafer, so that the following wafers (12) no longer need to be inspected. Using the measured results, the process parameters (31) of the process appliance (1) are automatically readjusted. Events such as maintenance work or parameter drifts in trend maps etc. are detected in control units (8 or 9) and, via the output of an event signal (102), for example in an event database (40), lead to the event-based selection of structure parameters (30′) to be measured and/or to the initiation of a leading wafer (11).

Abstract: There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.

Abstract: A lithographic tool can be adjusted by inspecting wafer images of an defect inspection tool and correlating the wafer images with images from a reference library in a database. Each reference image in the database corresponds to an initially measured amount of miss adjustment of lithographic tool parameters. The lithographic tool is adjusted automatically according to the reference image that is found to have the greatest resemblance to the wafer image. Time for adjusting is saved, operator staff needed is reduced, and objective determination criteria provide high wafer quality and yield.