Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

Abstract: Disclosed herein are genetic markers for animal growth, fatness, meat quality, and feed efficiency, methods for identifying such markers, and methods of screening animals to determine those more likely to produce desired growth, fatness, meat quality, and feed efficiency and preferably selecting those animals for future breeding purposes. The markers are based upon the presence or absence of certain polymorphisms in an HMGA nucleotide sequence.

Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

Abstract: Disclosed is a method and apparatus for an off boundary memory to provide off boundary memory access. The off boundary memory includes a right memory array having a plurality of right memory rows and a left memory array having a plurality of left memory rows. This forms a memory having a plurality of row lines, each row line having a right memory row and a left memory row, respectively. An off boundary row address decoder is coupled to both the right and left memory arrays and is capable of performing an off boundary memory access which includes accessing a desired plurality of memory addresses from one of a right or left memory row of a row line and from one of a left or right memory row of an adjacent row line at substantially the same time within one memory access cycle.

Abstract: Method and device intended for synchronized acquisition of seismic signals by one or more acquisition units suited for seismic signal digitizing, allowing to obtain, for each signal, a series y[n] of samples of these signals readjusted from a reference time on, from a first series x[n] of digitized samples of this seismic signal produced from any initial time prior to the reference time. The method essentially comprises detecting a synchronization signal indicative of this reference time (TR), measuring the effective time difference (D) between the reference time and the initial time, determining coefficients of a digital filter (F) suited to compensate for the fractional part (d) of the measured effective time difference, and applying this compensation digital filter to the first series of samples, which allows to obtain a series of digitized samples readjusted from the reference time.

Abstract: A method and apparatus for controlling a multiple chamber semiconductor wafer processing system. The processing system includes a plurality of process chambers about the periphery of the transfer chamber. A centrally located wafer transfer mechanism effects moving wafers between the process chambers. The process sequencer control is a real time, multi-tasking control program having a presequencer or look ahead feature for preventing delays in the processing. In one implementation, the look ahead feature identifies mid-sequence or oriented wafers which cannot be further processed because their destination chamber is busy. Rather than expend system resources waiting for the destination chamber to become available, the wafers are transferred to a holding position, preferably the load lock, and rescheduled at the earliest time to finish their processing.