Abstract: An exemplary method includes positioning a lead in a patient where the lead has a longitudinal axis that extends from a proximal end to a distal end and where the lead includes an electrode with an electrical center offset from the longitudinal axis of the lead body; measuring electrical potential in a three-dimensional potential field using the electrode; and based on the measuring and the offset of the electrical center, determining lead roll about the longitudinal axis of the lead body where lead roll may be used for correction of field heterogeneity, placement or navigation of the lead or physiological monitoring (e.g., cardiac function, respiration, etc.). Various other methods, devices, systems, etc., are also disclosed.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) for an integrated circuit includes a substrate of a first conductivity type, a first well region of a second conductivity type located in the substrate, and a second well region of the second conductivity type located within the substrate. The second well region is functionally connected to the first well region, and the second well region has a surface area greater than a surface area of the first well region. The MOSFET further includes a source of the first conductivity type located in the first well region, a drain of the first conductivity type located in the first well region, a substrate terminal of the second conductivity type located in the first well region, a gate oxide on a top surface of the first well region, and a gate electrode located on a top surface of the gate oxide.

Abstract: A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.

Abstract: A composite abrasive wheel comprises primary and secondary abrasive portions. The primary abrasive portion comprises shaped ceramic abrasive particles retained in a first organic binder. The secondary abrasive portion is bonded to the primary abrasive portion, and comprises secondary crushed abrasive particles retained in a second organic binder. The primary abrasive portion comprises a larger volume percentage of the shaped ceramic abrasive particles than the secondary abrasive portion. A central aperture extends through the composite abrasive wheel.

Abstract: Compositions and methods related to the removal of acidic gas. In one embodiment, compositions and methods are provided for the removal of acidic gas from a gas mixture using an aqueous amine solvent comprising water, a first amine, and a second amine, wherein the first amine contributes at least 50% by weight of the solvent's total amine concentration.

Abstract: This invention relates to novel quinoline compounds which affect gap junction activity. Also provided are methods of using such compounds and compositions containing the compounds to treat gap junction disorders.

Abstract: There is provided a copolymer having the general structure below, wherein a, b, and d are molar ratios varying between about 0.01 and about 0.90 and c is a molar ratio varying between about 0.01 and about 0.90; A1 represents monomer units comprising a cyano-containing pendant group in which the cyano is not directly attached to the backbone of the copolymer; A2 represents monomer units comprising two or more hydrogen bonding sites; A3 represents monomer units that increase solubility in organic solvents; and A4 represents monomer units that increase solubility in aqueous alkaline solutions. There is also provided a near-infrared radiation-sensitive coating composition comprising this copolymer as well as a positive-working thermal lithographic printing plate comprising a near-infrared radiation-sensitive coating comprising this copolymer, a method of producing such a printing plate, and finally a method of printing using such a printing plate. Formula (I).

Abstract: The present invention provides methods and compositions for increasing the seed size and/or seed number in plants. In particular, the methods and compositions provide for the over expression of a plant growth and/or development related or associated gene during embryo development. Transgenic plants transformed with genetic constructs having the plant growth and/or development associated gene under the control of an early phase-specific embryo promoter provides mature plants in the field that produce larger and/or more seeds. Methods for selection growth and development associated genes that provide transgenic plants with a higher yield phenotype are also provided.

Abstract: The present invention provides methods for transforming Camelina plants. In particular, the present invention relates to transforming Camelina sativa plants through contacting the plants to a dipping solution comprising Agrobacterium, a sugar, and a nonionic surfactant. The methods do not require a vacuum filtration step. The present invention provides, for example, useful methods for developing transformation systems for Camelina sativa that can enable manipulation of its agronomic qualities.

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.

Abstract: To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store digital data bits. SRAM memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle. To handle memory operations faster, a bit line multiplexing system is proposed. Two sets of bit lines are coupled to each memory cell and each set of bit lines are used for memory operations in alternating memory cycles. During a first memory cycle, a first set of bit lines accesses the memory array while precharging a second set of bit lines. Then during a second memory cycle following the first memory cycle, the first set of bit lines are precharged while the second set of bit lines accesses the memory array to read data.

Abstract: The present invention provides methods and compositions for increasing the seed size and/or seed number in plants. In particular, the methods and compositions provide for the over expression of a plant growth and/or development related or associated gene during embryo development. Transgenic plants transformed with genetic constructs having the plant growth and/or development associated gene under the control of an early phase-specific embryo promoter provides mature plants in the field that produce larger and/or more seeds. Methods for selection growth and development associated genes that provide transgenic plants with a higher yield phenotype are also provided.

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Abstract: To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

Abstract: An exemplary method includes accessing cardiac information acquired via a catheter located at various positions in a venous network of a heart of a patient wherein the cardiac information comprises position information with respect to time for one or more electrodes of the catheter; performing a principal component analysis on at least some of the position information; and selecting at least one component of the principal component analysis to represent an axis of a cardiac coordinate system. Various other methods, devices, systems, etc., are also disclosed.

Abstract: During execution of an existing scheduling computer program on a client node, an update computer program and a self-describing automatic installation package are downloaded to the client node from a logical depot node implemented on an existing management server. Therefore, advantageously, no physical depot node or other additional computing device is needed for the client node to update itself. Execution of the update computer program is spawned on the client node from the existing scheduling computer program. As such, the update computer program inherits root access to the client node and security credentials to the management server from the scheduling computer program—advantageously, then, a user does not have to perform any laborious configuration of the client node in order to update the node. The client node ultimately updates itself using the self-describing automatic installation package, which includes all the information needed for the client node to update itself.

Abstract: An exemplary method includes selecting a first pair of electrodes to define a first vector and selecting a second pair of electrodes to define a second vector; acquiring position information during one or more cardiac cycles for the first and second pairs of electrodes wherein the acquiring comprises using each of the electrodes for measuring one or more electrical potentials in an electrical localization field established in the patient; and determining a dyssynchrony index by applying a cross-covariance technique to the position information for the first and the second vectors. Another method includes determining a phase shift based on the acquired position information for the first and the second vectors; and determining an interventricular delay based at least in part on the phase shift.

Abstract: A method includes selecting an electrode located in a patient; acquiring position information with respect to time for the electrode where the acquiring uses the electrode for repeatedly measuring electrical potentials in an electrical localization field established in the patient; calculating a stability metric for the electrode based on the acquired position information with respect to time; and deciding if the selected electrode, as located in the patient, has a stable location for sensing biological electrical activity, for delivering electrical energy or for sensing biological electrical activity and delivering electrical energy. Position information may be acquired during one or both of intrinsic or paced activation of a heart and respective stability indexes calculated for each activation type.

Abstract: A conductive sleeved fastener assembly includes an electrically-conductive fastener having a fastener head and a fastener shank extending from the fastener head and an electrically-conductive fastener sleeve receiving the fastener shank of the fastener and a fastener sleeve flange provided on the fastener sleeve and disposed in direct contact with the fastener head of the fastener. A method of preparing a conductive sleeved fastener for use is also disclosed.